4.28 Assembly language changes after RVCT v2.1

The assembler accepts ARM and Thumb instructions written in either UAL or pre-UAL syntax. Some older versions of the assembler only accept pre-UAL syntax.

The assembly language accepted by the RVCT v2.1 assembler and earlier is called pre-UAL ARM and Thumb. In RVCT 2.2 and later, the assembler accepts both the UAL and the pre-UAL ARM and Thumb syntax. The assembler accepts the pre-UAL Thumb syntax only if it is preceded by a CODE16 directive, or if the source file is assembled with the --16 command-line option.

For the convenience of programmers who are familiar with the ARM assembly language accepted in RVCT v2.1 and earlier, the following table highlights the differences between the UAL and pre-UAL ARM assembly language syntax:

Table 4-3 Changes from earlier ARM assembly language

Change Pre-UAL ARM syntax Preferred UAL syntax
The default addressing mode for LDM and STM is IA
You can use the PUSH and POP mnemonics for full, descending stack operations in ARM in addition to Thumb.
STMFD sp!, {reglist}
LDMFD sp!, {reglist}
PUSH {reglist}
POP {reglist}
You can use the LSL, LSR, ASR, ROR, and RRX instruction mnemonics for instructions with rotations and no other operation, in ARM in addition to Thumb.
MOV Rd, Rn, LSL shift
MOV Rd, Rn, LSR shift
MOV Rd, Rn, ASR shift
MOV Rd, Rn, ROR shift
LSL Rd, Rn, shift
LSR Rd, Rn, shift
ASR Rd, Rn, shift
ROR Rd, Rn, shift
RRX Rd, Rn
Use the label form for PC-relative addressing. Do not use the offset form in new code.
LDR Rd, [pc, #offset]
LDR Rd, label
Specify both registers for doubleword memory accesses. You must still obey rules about the register combinations you can use.
LDRD Rd, addr_mode
LDRD Rd, Rd2, addr_mode
{cond}, if used, is always the last element of all instructions.

In addition, some flexibility is permitted that was not permitted in previous assemblers as the following table shows:

Table 4-4 Relaxation of requirements

Relaxation Permitted syntax Preferred syntax
If the destination register is the same as the first operand, you can use a two register form of the instruction.
ADD r1, r3
ADD r1, r1, r3

You can write source code for Thumb processors earlier than ARMv6T2 using UAL.

If you are writing Thumb code for a processor earlier than ARMv6T2, you must restrict yourself to instructions that are available on the processor. The assembler generates error messages if you attempt to use an instruction that is not available.

If you are writing Thumb code for an ARMv6T2 or later processor, you can minimize your code size by using 16-bit instructions wherever possible.

The following table shows the main differences between the UAL and the pre-UAL Thumb assembly language:

Table 4-5 Differences between pre-UAL Thumb syntax and UAL syntax

Change Pre-UAL Thumb syntax UAL syntax
The default addressing mode for LDM and STM is IA LDMIA, STMIA LDM, STM
You must use the S postfix on instructions that update the flags. This change is essential to avoid conflict with 32-bit Thumb instructions.
ADD r1, r2, r3
SUB r4, r5, #6
MOV r0, #1
LSR r1, r2, #1
ADDS r1, r2, r3
SUBS r4, r5, #6
MOVS r0, #1
LSRS r1, r2, #1
The preferred form for ALU instructions specifies three registers, even if the destination register is the same as the first operand. However, the UAL syntax allows the two register syntax.
ADD r7, r8
SUB r1, #80
ADD r7, r7, r8
SUBS r1, r1, #80
If Rd and Rn are both Lo registers, MOV Rd, Rn is disassembled as ADDS Rd, Rn, #0.
MOV r2, r3
MOV r8, r9
CPY r0, r1
LSL r2, r3, #0
ADDS r2, r3, #0
MOV r8, r9
MOV r0, r1
MOVS r2, r3
NEG Rd, Rm is disassembled as RSBS Rd, Rm, #0. NEG Rd, Rm RSBS Rd, Rm, #0
When using the LDR Rd,=const literal load pseudo-instruction, in pre-UAL syntax, the generated instruction might affect the condition code flags.

In UAL syntax, the generated instruction sequence is guaranteed to not affect the condition code flags.

LDR r0,=0
; generates the instruction:
MOVS r0,#0
LDR r0,=0
; generates the sequence:
LDR r0,{pc}+n
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