Non-Confidential | PDF version | ARM DUI0473M | ||
| ||||
Home > ARM and Thumb Instructions > ARM and Thumb instruction summary |
Different ARM architectures support different sets of ARM and Thumb instructions.
The following table gives a summary of the availability of ARM and Thumb instructions in different versions of the ARM architecture:
Table 11-1 Summary of ARM and Thumb instructions
Mnemonic | Brief description | Arch. |
---|---|---|
ADC |
Add with Carry | All |
ADD |
Add | All |
ADR |
Load program or register-relative address (short range) | All |
ADRL pseudo-instruction |
Load program or register-relative address (medium range) | x6M |
AND |
Logical AND | All |
ASR |
Arithmetic Shift Right | All |
B |
Branch | All |
BFC |
Bit Field Clear | T2 |
BFI |
Bit Field Insert | T2 |
BIC |
Bit Clear | All |
BKPT |
Breakpoint | 5 |
BL |
Branch with Link | All |
BLX |
Branch with Link, change instruction set | T |
BX |
Branch, change instruction set | T |
BXJ |
Branch, change to Jazelle^{®} | J, x7M |
CBZ, CBNZ |
Compare and Branch if {Non}Zero | T2 |
CDP |
Coprocessor Data Processing operation | x6M |
CDP2 |
Coprocessor Data Processing operation | 5, x6M |
CLREX |
Clear Exclusive | K, x6M |
CLZ |
Count leading zeros | 5, x6M |
CMN , CMP |
Compare Negative, Compare | All |
CPS |
Change Processor State | 6 |
CPY pseudo-instruction |
Copy | 6 |
DBG |
Debug | 7 |
DMB |
Data Memory Barrier | 7, 6M |
DSB |
Data Synchronization Barrier | 7, 6M |
EOR |
Exclusive OR | All |
ERET |
Exception Return | 7VE |
HVC |
Hypervisor Call | 7VE |
ISB |
Instruction Synchronization Barrier | 7, 6M |
IT |
If-Then | T2 |
LDC |
Load Coprocessor | x6M |
LDC2 |
Load Coprocessor | 5, x6M |
LDM |
Load Multiple registers | All |
LDR |
Load Register with word | All |
LDR pseudo-instruction |
Load Register pseudo-instruction | All |
LDRB |
Load Register with byte | All |
LDRBT |
Load Register with byte, user mode | x6M |
LDRD |
Load Registers with two words | 5E, x6M |
LDREX |
Load Register Exclusive | 6, x6M |
LDREXB , LDREXH |
Load Register Exclusive Byte, Halfword | K, x6M |
LDREXD |
Load Register Exclusive Doubleword | K, x7M |
LDRH |
Load Register with halfword | All |
LDRHT |
Load Register with halfword, user mode | T2 |
LDRSB |
Load Register with signed byte | All |
LDRSBT |
Load Register with signed byte, user mode | T2 |
LDRSH |
Load Register with signed halfword | All |
LDRSHT |
Load Register with signed halfword, user mode | T2 |
LDRT |
Load Register with word, user mode | x6M |
LSL |
Logical Shift Left | All |
LSR |
Logical Shift Right | All |
MAR |
Move from Registers to 40-bit Accumulator | XScale |
MCR |
Move from Register to Coprocessor | x6M |
MCR2 |
Move from Register to Coprocessor | 5, x6M |
MCRR |
Move from Registers to Coprocessor | 5E, x6M |
MCRR2 |
Move from Registers to Coprocessor | 6, x6M |
MIA , MIAPH , MIAxy |
Multiply with Internal 40-bit Accumulate | XScale |
MLA |
Multiply Accumulate | x6M |
MLS |
Multiply and Subtract | T2 |
MOV |
Move | All |
MOVT |
Move Top | T2 |
MOV32 pseudo-instruction |
Move 32-bit immediate to register | T2 |
MRA |
Move from 40-bit Accumulator to Registers | XScale |
MRC |
Move from Coprocessor to Register | x6M |
MRC2 |
Move from Coprocessor to Register | 5, x6M |
MRRC |
Move from Coprocessor to Registers | 5E, x6M |
MRRC2 |
Move from Coprocessor to Registers | 6, x6M |
MRS |
Move from PSR to register | All |
MRS |
Move from system Coprocessor to Register | 7A, 7R |
MSR |
Move from register to PSR | All |
MSR |
Move from Register to system Coprocessor | 7A, 7R |
MUL |
Multiply | All |
MVN |
Move Not | All |
NEG pseudo-instruction |
Negate | All |
NOP |
No Operation | All |
ORN |
Logical OR NOT | T2 |
ORR |
Logical OR | All |
PKHBT , PKHTB |
Pack Halfwords | 6, 7EM |
PLD |
Preload Data | 5E, x6M |
PLDW |
Preload Data with intent to Write | 7MP |
PLI |
Preload Instruction | 7 |
POP |
POP registers from stack | All |
PUSH |
PUSH registers to stack | All |
QADD |
Signed saturating Add | 5E, 7EM |
QADD8 |
Signed saturating parallel byte-wise addition | 6, 7EM |
QADD16 |
Signed saturating parallel halfword-wise addition | 6, 7EM |
QASX |
Signed saturating parallel add and subtract halfwords with exchange | 6, 7EM |
QDADD |
Signed saturating Double and Add | 5E, 7EM |
QDSUB |
Signed saturating Double and Subtract | 5E, 7EM |
QSAX |
Signed saturating parallel subtract and add halfwords with exchange | 6, 7EM |
QSUB |
Signed saturating Subtract | 5E, 7EM |
QSUB8 |
Signed saturating parallel byte-wise subtraction | 6, 7EM |
QSUB16 |
Signed saturating parallel halfword-wise subtraction | 6, 7EM |
RBIT |
Reverse Bits | T2 |
REV |
Reverse byte order in a word | 6 |
REV16 |
Reverse byte order in two halfwords | 6 |
REVSH |
Reverse byte order in a halfword and sign extend | 6 |
RFE |
Return From Exception | T2, x7M |
ROR |
Rotate Right Register | All |
RRX |
Rotate Right with Extend | x6M |
RSB |
Reverse Subtract | All |
RSC |
Reverse Subtract with Carry | x7M |
SADD8 |
Signed parallel byte-wise addition | 6, 7EM |
SADD16 |
Signed parallel halfword-wise addition | 6, 7EM |
SASX |
Signed parallel add and subtract halfwords with exchange | 6, 7EM |
SBC |
Subtract with Carry | All |
SBFX |
Signed Bit Field eXtract | T2 |
SDIV |
Signed divide | 7A, 7M, 7R |
SEL |
Select bytes according to APSR GE flags | 6, 7EM |
SETEND |
Set Endianness for memory accesses | 6, x7M |
SEV |
Set Event | K, 6M |
SHADD8 |
Signed halving parallel byte-wise addition | 6, 7EM |
SHADD16 |
Signed halving parallel halfword-wise addition | 6, 7EM |
SHASX |
Signed halving parallel add and subtract halfwords with exchange | 6, 7EM |
SHSAX |
Signed halving parallel subtract and add halfwords with exchange | 6, 7EM |
SHSUB8 |
Signed halving parallel byte-wise subtraction | 6, 7EM |
SHSUB16 |
Signed halving parallel halfword-wise subtraction | 6, 7EM |
SMC |
Secure Monitor Call | Z |
SMLAxy |
Signed Multiply with Accumulate (32 <= 16 x 16 + 32) | 5E, 7EM |
SMLAD |
Dual Signed Multiply Accumulate | 6, 7EM |
(32 <= 32 + 16 x 16 + 16 x 16) | ||
SMLAL |
Signed Multiply Accumulate (64 <= 64 + 32 x 32) | x6M |
SMLALxy |
Signed Multiply Accumulate (64 <= 64 + 16 x 16) | 5E, 7EM |
SMLALD |
Dual Signed Multiply Accumulate Long | 6, 7EM |
(64 <= 64 + 16 x 16 + 16 x 16) | ||
SMLAWy |
Signed Multiply with Accumulate (32 <= 32 x 16 + 32) | 5E, 7EM |
SMLSD |
Dual Signed Multiply Subtract Accumulate | 6, 7EM |
(32 <= 32 + 16 x 16 – 16 x 16) | ||
SMLSLD |
Dual Signed Multiply Subtract Accumulate Long | 6, 7EM |
(64 <= 64 + 16 x 16 – 16 x 16) | ||
SMMLA |
Signed top word Multiply with Accumulate (32 <= TopWord(32 x 32 + 32)) | 6, 7EM |
SMMLS |
Signed top word Multiply with Subtract (32 <= TopWord(32 - 32 x 32)) | 6, 7EM |
SMMUL |
Signed top word Multiply (32 <= TopWord(32 x 32)) | 6, 7EM |
SMUAD , SMUSD |
Dual Signed Multiply, and Add or Subtract products | 6, 7EM |
SMULxy |
Signed Multiply (32 <= 16 x 16) | 5E, 7EM |
SMULL |
Signed Multiply (64 <= 32 x 32) | x6M |
SMULWy |
Signed Multiply (32 <= 32 x 16) | 5E, 7EM |
SRS |
Store Return State | T2, x7M |
SSAT |
Signed Saturate | 6, x6M |
SSAT16 |
Signed Saturate, parallel halfwords | 6, 7EM |
SSAX |
Signed parallel subtract and add halfwords with exchange | 6, 7EM |
SSUB8 |
Signed parallel byte-wise subtraction | 6, 7EM |
SSUB16 |
Signed parallel halfword-wise subtraction | 6, 7EM |
STC |
Store Coprocessor | x6M |
STC2 |
Store Coprocessor | 5, x6M |
STM |
Store Multiple registers | All |
STR |
Store Register with word | All |
STRB |
Store Register with byte | All |
STRBT |
Store Register with byte, user mode | x6M |
STRD |
Store Registers with two words | 5E, x6M |
STREX |
Store Register Exclusive | 6, x6M |
STREXB , STREXH |
Store Register Exclusive Byte, Halfword | K, x6M |
STREXD |
Store Register Exclusive Doubleword | K, x7M |
STRH |
Store Register with halfword | All |
STRHT |
Store Register with halfword, user mode | T2 |
STRT |
Store Register with word, user mode | x6M |
SUB |
Subtract | All |
SUBS pc, lr |
Exception return, no stack | T2, x7M |
SVC (formerly SWI ) |
SuperVisor Call | All |
SWP , SWPB |
Swap registers and memory (ARM only) | All, x7M |
SXTAB |
Sign extend Byte, with Addition | 6, 7EM |
SXTAB16 |
Sign extend two Bytes, with Addition | 6, 7EM |
SXTAH |
Sign extend Halfword, with Addition | 6, 7EM |
SXTB |
Sign extend Byte | 6 |
SXTH |
Sign extend Halfword | 6 |
SXTB16 |
Sign extend two Bytes | 6, 7EM |
SYS |
Execute system coprocessor instruction | 7A, 7R |
TBB , TBH |
Table Branch Byte, Halfword | T2 |
TEQ |
Test Equivalence | x6M |
TST |
Test | All |
UADD8 |
Unsigned parallel byte-wise addition | 6, 7EM |
UADD16 |
Unsigned parallel halfword-wise addition | |
UASX |
Unsigned parallel add and subtract halfwords with exchange | |
UBFX |
Unsigned Bit Field eXtract | T2 |
UDIV |
Unsigned divide | 7A, 7M, 7R |
UHADD8 |
Unsigned halving parallel byte-wise addition | 6, 7EM |
UHADD16 |
Unsigned halving parallel halfword-wise addition | 6, 7EM |
UHASX |
Unsigned halving parallel add and subtract halfwords with exchange | 6, 7EM |
UHSAX |
Unsigned halving parallel subtract and add halfwords with exchange | 6, 7EM |
UHSUB8 |
Unsigned halving parallel byte-wise subtraction | 6, 7EM |
UHSUB16 |
Unsigned halving parallel halfword-wise subtraction | 6, 7EM |
UMAAL |
Unsigned Multiply Accumulate Accumulate Long | 6, 7EM |
(64 <= 32 + 32 + 32 x 32) | ||
UMLAL |
Unsigned Multiply Accumulate | x6M |
(64 <= 32 x 32 + 64), (64 <= 32 x 32) | ||
UMULL |
Unsigned Multiply | x6M |
(64 <= 32 x 32 + 64), (64 <= 32 x 32) | ||
UQADD8 |
Unsigned saturating parallel byte-wise addition | 6, 7EM |
UQADD16 |
Unsigned saturating parallel halfword-wise addition | 6, 7EM |
UQASX |
Unsigned saturating parallel add and subtract halfwords with exchange | 6, 7EM |
UQSAX |
Unsigned saturating parallel subtract and add halfwords with exchange | 6, 7EM |
UQSUB8 |
Unsigned saturating parallel byte-wise subtraction | 6, 7EM |
UQSUB16 |
Unsigned saturating parallel halfword-wise subtraction | 6, 7EM |
USAD8 |
Unsigned Sum of Absolute Differences | 6, 7EM |
USADA8 |
Accumulate Unsigned Sum of Absolute Differences | 6, 7EM |
USAT |
Unsigned Saturate | 6, x6M |
USAT16 |
Unsigned Saturate, parallel halfwords | 6, 7EM |
USAX |
Unsigned parallel subtract and add halfwords with exchange | 6, 7EM |
USUB8 |
Unsigned parallel byte-wise subtraction | 6, 7EM |
USUB16 |
Unsigned parallel halfword-wise subtraction | 6, 7EM |
UXTAB |
Zero extend Byte with Addition | 6, 7EM |
UXTAB16 |
Zero extend two bytes with Addition | 6, 7EM |
UXTAH |
Zero extend Halfword with Addition | 6, 7EM |
UXTB |
Zero extend Byte | 6 |
UXTH |
Zero extend Halfword | 6 |
UXTB16 |
Zero extend two bytes | 6, 7EM |
V* |
NEON and VFP instructions | |
WFE |
Wait For Event | T2, 6M |
WFI |
Wait For Interrupt | T2, 6M |
YIELD |
Yield | T2, 6M |
Entries in the Architecture column indicate that the instructions are available as follows:
All versions of the ARM architecture.
The ARMv5T*, ARMv6*, and ARMv7 architectures.
The ARMv5TE, ARMv6*, and ARMv7 architectures.
The ARMv6* and ARMv7 architectures.
The ARMv6-M and ARMv7 architectures.
Not available in the ARMv6-M architecture.
The ARMv7 architectures.
The ARMv7-A architecture.
The ARMv7-M architecture, including ARMv7E-M implementations.
Not available in the ARMv6-M or ARMv7-M architecture, or any ARMv7E-M implementation.
ARMv7E-M implementations but not in the ARMv7-M or ARMv6-M architecture.
The ARMv7-R architecture.
The ARMv7 architectures that implement the Multiprocessing Extensions.
The ARMv7 architectures that implement the Virtualization Extensions.
The ARMv5TEJ, ARMv6*, and ARMv7 architectures.
The ARMv6K, and ARMv7 architectures.
The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.
The ARMv6T2 and above architectures.
XScale versions of the ARM architecture.
If Security Extensions are implemented.