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Register shift operations move the bits in a register left or right by a specified number of bits, called the shift length.
Register shift can be performed:
Directly by the instructions ASR
, LSR
, LSL
,
ROR
, and RRX
, and the result is written to a
destination register.
During the calculation of Operand2
by the instructions that specify the second
operand as a register with shift. The result is used by the instruction.
The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or the flexible second operand description. If the shift length is 0, no shift occurs. Register shift operations update the carry flag except when the specified shift length is 0.
Arithmetic shift right by n bits moves the left-hand 32-n bits of a register to the right by n places, into the right-hand 32-n bits of the result. It copies the original bit[31] of the register into the left-hand n bits of the result.
You can use the ASR #
operation to divide the value in
the register n
Rm
by 2^{n}, with the result
being rounded towards negative-infinity.
When the instruction is ASRS
or when ASR
#
is used in n
Operand2
with the
instructions MOVS
, MVNS
, ANDS
,
ORRS
, ORNS
, EORS
,
BICS
, TEQ
or TST
, the carry flag is
updated to the last bit shifted out, bit[n
-1], of the register
Rm
.
If n
is 32 or more, then all the bits in the result are set to the
value of bit[31] of Rm
.
If n
is 32 or more and the carry flag is updated, it is updated to
the value of bit[31] of Rm
.
Logical shift right by n bits moves the left-hand 32-n bits of a register to the right by n places, into the right-hand 32-n bits of the result. It sets the left-hand n bits of the result to 0.
You can use the LSR #
operation to divide the value in
the register n
Rm
by 2^{n}, if the value is
regarded as an unsigned integer.
When the instruction is LSRS
or when LSR
#
is used in n
Operand2
with the
instructions MOVS
, MVNS
, ANDS
,
ORRS
, ORNS
, EORS
,
BICS
, TEQ
or TST
, the carry flag is
updated to the last bit shifted out, bit[n
-1], of the register
Rm
.
If n
is 32 or more, then all the bits in the result are cleared to
0.
If n
is 33 or more and the carry flag is updated, it is updated to
0.
Logical shift left by n bits moves the right-hand 32-n bits of a register to the left by n
places, into the left-hand 32-n bits of the result. It sets the right-hand
bits of the result to 0.n
You can use the LSL #
operation to multiply the value
in the register n
Rm
by 2^{n}, if the value is
regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur
without warning.
When the instruction is LSLS
or when LSL
#
, with non-zero n
n
, is used in
Operand2
with the instructions MOVS
,
MVNS
, ANDS
, ORRS
,
ORNS
, EORS
, BICS
, TEQ
or
TST
, the carry flag is updated to the last bit shifted out,
bit[32
-n
], of the register Rm
.
These instructions do not affect the carry flag when used with LSL
#0.
If n
is 32 or more, then all the bits in the result are cleared to
0.
If n
is 33 or more and the carry flag is updated, it is updated to
0.
Rotate right by n bits moves the left-hand 32-n bits of a register to the right by n places, into the right-hand 32-n bits of the result. It also moves the right-hand n bits of the register into the left-hand n bits of the result.
When the instruction is RORS
or when ROR
#
is used in n
Operand2
with the
instructions MOVS
, MVNS
, ANDS
,
ORRS
, ORNS
, EORS
,
BICS
, TEQ
or TST
, the carry flag is
updated to the last bit rotation, bit[n
-1], of the register
Rm
.
If n
is 32, then the value of the result is same as the value in
Rm
, and if the carry flag is updated, it is updated to bit[31] of
Rm
.
ROR
with shift length, n
, more than 32 is the
same as ROR
with shift length n
-32.
Rotate right with extend moves the bits of a register to the right by one bit. It copies the carry flag into bit[31] of the result.
When the instruction is RRXS
or when RRX is used in
Operand2
with the instructions MOVS
,
MVNS
, ANDS
, ORRS
,
ORNS
, EORS
, BICS
, TEQ
or
TST
, the carry flag is updated to bit[0] of the register
Rm
.