11.14 AND

Logical AND.

Syntax

AND{S}{cond} Rd, Rn, Operand2

where:

S

is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand.

Operation

The AND instruction performs bitwise AND operations on the values in Rn and Operand2.

In certain circumstances, the assembler can substitute BIC for AND, or AND for BIC. Be aware of this when reading disassembly listings.

Use of PC in Thumb instructions

You cannot use PC (R15) for Rd or any operand with the AND instruction.

Use of PC and SP in ARM instructions

You can use PC and SP with the AND ARM instruction but this is deprecated in ARMv6T2 and above.

If you use PC as Rn, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.

Condition flags

If S is specified, the AND instruction:

  • Updates the N and Z flags according to the result.

  • Can update the C flag during the calculation of Operand2.

  • Does not affect the V flag.

16-bit instructions

The following forms of this instruction are available in Thumb code, and are 16-bit instructions:

ANDS Rd, Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used outside an IT block.

AND{cond} Rd, Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used inside an IT block.

It does not matter if you specify AND{S} Rd, Rm, Rd. The instruction is the same.

Examples

    AND     r9,r2,#0xFF00
    ANDS    r9, r8, #0x19
Non-ConfidentialPDF file icon PDF versionARM DUI0473M
Copyright © 2010-2016 ARM Limited or its affiliates. All rights reserved.