11.17 BFC

Bit Field Clear.

Syntax

BFC{cond} Rd, #lsb, #width

where:

cond

is an optional condition code.

Rd

is the destination register.

lsb

is the least significant bit that is to be cleared.

width

is the number of bits to be cleared. width must not be 0, and (width+lsb) must be less than or equal to 32.

Operation

Clears adjacent bits in a register. width bits in Rd are cleared, starting at lsb. Other bits in Rd are unchanged.

Register restrictions

You cannot use PC for any register.

You can use SP in the BFC ARM instruction but this is deprecated in ARMv6T2 and above. You cannot use SP in the BFC Thumb instruction.

Condition flags

The BFC instruction does not change the flags.

Architectures

This ARM instruction is available in ARMv6T2 and above.

This 32-bit Thumb instruction is available in ARMv6T2 and above.

There is no 16-bit version of this instruction in Thumb.

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