11.23 BX

Branch and exchange instruction set.

Syntax

BX{cond} Rm

where:

cond

is an optional condition code. cond is not available on all forms of this instruction.

Rm

is a register containing an address to branch to.

Operation

The BX instruction causes a branch to the address contained in Rm and exchanges the instruction set, if required:

  • BX Rm derives the target instruction set from bit[0] of Rm:

    • If bit[0] of Rm is 0, the processor changes to, or remains in, ARM state.

    • If bit[0] of Rm is 1, the processor changes to, or remains in, Thumb state.

Instruction availability and branch ranges

The following table shows the instructions that are available in ARM and Thumb state. Instructions that are not shown in this table are not available. Notes in brackets show the first architecture version where the instruction is available.

Table 11-8 BX instruction availability and range

Instruction ARM   Thumb, 16-bit encoding Thumb, 32-bit encoding
BX Rm a Available (4T, 5) Available (All T) Use 16-bit (All T2)
BX{cond} Rm a Available (4T, 5) -   - -

Register restrictions

You can use PC for Rm in the ARM BX instruction, but this is deprecated in ARMv6T2 and above. You cannot use PC in other ARM instructions.

You can use PC for Rm in the Thumb BX instruction. You cannot use PC in other Thumb instructions.

You can use SP for Rm in the ARM BX instruction but this is deprecated in ARMv6T2 and above.

You can use SP for Rm in the Thumb BX instruction, but this is deprecated.

Condition flags

The BX instruction does not change the flags.

Architectures

See the preceding table for details of availability of the BX instruction in each architecture.

a 

The assembler accepts BX{cond} Rm for code assembled for ARMv4 and converts it to MOV{cond} PC, Rm at link time, unless objects targeted for ARMv4T are present.

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