11.35 EOR

Logical Exclusive OR.

Syntax

EOR{S}{cond} Rd, Rn, Operand2

where:

S

is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand.

Operation

The EOR instruction performs bitwise Exclusive OR operations on the values in Rn and Operand2.

Use of PC in Thumb instructions

You cannot use PC (R15) for Rd or any operand in an EOR instruction.

Use of PC and SP in ARM instructions

You can use PC and SP with the EOR instruction but they are deprecated in ARMv6T2 and above.

If you use PC as Rn, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.

Condition flags

If S is specified, the EOR instruction:

  • Updates the N and Z flags according to the result.

  • Can update the C flag during the calculation of Operand2.

  • Does not affect the V flag.

16-bit instructions

The following forms of the EOR instruction are available in Thumb code, and are 16-bit instructions:

EORS Rd, Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used outside an IT block.

EOR{cond} Rd, Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used inside an IT block.

It does not matter if you specify EOR{S} Rd, Rm, Rd. The instruction is the same.

Correct examples

    EORS    r0,r0,r3,ROR r6
    EORS    r7, r11, #0x18181818 

Incorrect example

    EORS    r0,pc,r3,ROR r6     ; PC not permitted with register
                                ; controlled shift
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