11.42 LDR (immediate offset)

Load with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

Syntax

LDR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset

LDR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed

LDR{type}{cond} Rt, [Rn], #offset ; post-indexed

LDRD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, doubleword

LDRD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, doubleword

LDRD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, doubleword

where:

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code.

Rt

is the register to load.

Rn

is the register on which the memory address is based.

offset

is an offset. If offset is omitted, the address is the contents of Rn.

Rt2

is the additional register to load for doubleword operations.

Not all options are available in every instruction set and architecture.

Offset ranges and architectures

The following table shows the ranges of offsets and availability of these instructions:

Table 11-10 Offsets and architectures, LDR, word, halfword, and byte

Instruction Immediate offset Pre-indexed Post-indexed Arch.
ARM, word or byte a –4095 to 4095 –4095 to 4095 –4095 to 4095 All
ARM, signed byte, halfword, or signed halfword –255 to 255 –255 to 255 –255 to 255 All
ARM, doubleword –255 to 255 –255 to 255 –255 to 255 5E
Thumb 32-bit encoding, word, halfword, signed halfword, byte, or signed byte a –255 to 4095 –255 to 255 –255 to 255 T2
Thumb 32-bit encoding, doubleword –1020 to 1020 b –1020 to 1020 b –1020 to 1020 b T2
Thumb 16-bit encoding, word c 0 to 124 b Not available Not available T
Thumb 16-bit encoding, unsigned halfword c 0 to 62 d Not available Not available T
Thumb 16-bit encoding, unsigned byte c 0 to 31 Not available Not available T
Thumb 16-bit encoding, word, Rn is SP e 0 to 1020 b Not available Not available T

Notes about the Architectures column

Entries in the Architecture column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

5E

The ARMv5TE, ARMv6*, and ARMv7 architectures.

T2

The ARMv6T2 and above architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

Register restrictions

Rn must be different from Rt in the pre-index and post-index forms.

Doubleword register restrictions

Rn must be different from Rt2 in the pre-index and post-index forms.

For Thumb instructions, you must not specify SP or PC for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register.

  • Rt must not be LR.

  • ARM strongly recommends that you do not use R12 for Rt.

  • Rt2 must be R(t + 1).

Use of PC

In ARM code you can use PC for Rt in LDR word instructions and PC for Rn in LDR instructions.

Other uses of PC are not permitted in these ARM instructions.

In Thumb code you can use PC for Rt in LDR word instructions and PC for Rn in LDR instructions. Other uses of PC in these Thumb instructions are not permitted.

Use of SP

You can use SP for Rn.

In ARM code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word instructions in ARM code but this is deprecated in ARMv6T2 and above.

In Thumb code, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in Thumb code.

Examples

    LDR     r8,[r10]        ; loads R8 from the address in R10.
    LDRNE   r2,[r5,#960]!   ; (conditionally) loads R2 from a word
                            ; 960 bytes above the address in R5, and
                            ; increments R5 by 960.
a 

For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

b 

Must be divisible by 4.

c 

Rt and Rn must be in the range R0-R7.

d 

Must be divisible by 2.

e 

Rt must be in the range R0-R7.

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