11.44 LDR (register offset)

Load with register offset, pre-indexed register offset, or post-indexed register offset.

Syntax

LDR{type}{cond} Rt, [Rn, ±Rm {, shift}] ; register offset

LDR{type}{cond} Rt, [Rn, ±Rm {, shift}]! ; pre-indexed ; ARM only

LDR{type}{cond} Rt, [Rn], ±Rm {, shift} ; post-indexed ; ARM only

LDRD{cond} Rt, Rt2, [Rn, ±Rm] ; register offset, doubleword ; ARM only

LDRD{cond} Rt, Rt2, [Rn, ±Rm]! ; pre-indexed, doubleword ; ARM only

LDRD{cond} Rt, Rt2, [Rn], ±Rm ; post-indexed, doubleword ; ARM only

where:

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code.

Rt

is the register to load.

Rn

is the register on which the memory address is based.

Rm

is a register containing a value to be used as the offset. –Rm is not permitted in Thumb code.

shift

is an optional shift.

Rt2

is the additional register to load for doubleword operations.

Not all options are available in every instruction set and architecture.

Offset register and shift options

The following table shows the ranges of offsets and availability of these instructions:

Table 11-12 Options and architectures, LDR (register offsets)

Instruction +/–Rm a shift     Arch.
ARM, word or byte b +/–Rm LSL #0-31 LSR #1-32   All
    ASR #1-32 ROR #1-31 RRX  
ARM, signed byte, halfword, or signed halfword +/–Rm Not available All
ARM, doubleword +/–Rm Not available 5E
Thumb 32-bit encoding, word, halfword, signed halfword, byte, or signed byte b +Rm LSL #0-3     T2
Thumb 16-bit encoding, all except doubleword c +Rm Not available T

Notes about the Architecture column

Entries in the Architecture column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

5E

The ARMv5TE, ARMv6*, and ARMv7 architectures.

T2

The ARMv6T2 and above architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

Register restrictions

In the pre-index and post-index forms:

  • Rn must be different from Rt.

  • Rn must be different from Rm in architectures before ARMv6.

Doubleword register restrictions

For ARM instructions:

  • Rt must be an even-numbered register.

  • Rt must not be LR.

  • ARM strongly recommends that you do not use R12 for Rt.

  • Rt2 must be R(t + 1).

  • Rm must be different from Rt and Rt2 in LDRD instructions.

  • Rn must be different from Rt2 in the pre-index and post-index forms.

Use of PC

In ARM instructions you can use PC for Rt in LDR word instructions, and you can use PC for Rn in LDR instructions with register offset syntax (that is the forms that do not writeback to the Rn).

Other uses of PC are not permitted in ARM instructions.

In Thumb instructions you can use PC for Rt in LDR word instructions. Other uses of PC in these Thumb instructions are not permitted.

Use of SP

You can use SP for Rn.

In ARM code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word ARM instructions but this is deprecated in ARMv6T2 and above.

You can use SP for Rm in ARM instructions but this is deprecated in ARMv6T2 and above.

In Thumb code, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in Thumb code.

Use of SP for Rm is not permitted in Thumb state.

a 

Where +/–Rm is shown, you can use –Rm, +Rm, or Rm. Where +Rm is shown, you cannot use –Rm.

b 

For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

c 

Rt, Rn, and Rm must all be in the range R0-R7.

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