11.45 LDR (register-relative)

Load register. The address is an offset from a base register.

Syntax

LDR{type}{cond}{.W} Rt, label

LDRD{cond} Rt, Rt2, label ; Doubleword

where:

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code.

.W

is an optional instruction width specifier.

Rt

is the register to load or store.

Rt2

is the second register to load or store.

label

is a symbol defined by the FIELD directive. label specifies an offset from the base register which is defined using the MAP directive.

label must be within a limited distance of the value in the base register.

Offset range and architectures

The assembler calculates the offset from the base register for you. The assembler generates an error if label is out of range.

The following table shows the possible offsets between the label and the current instruction:

Table 11-13 Register-relative offsets

Instruction Offset range Architectures
ARM LDR, LDRB a +/– 4095 All
ARM LDRSB, LDRH, LDRSH +/– 255 All
ARM LDRD +/– 255 5E
Thumb, 32-bit LDR, LDRB, LDRSB, LDRH, LDRSH a –255 to 4095 T2
Thumb, 32-bit LDRD +/– 1020 b T2
Thumb, 16-bit LDR c 0 to 124 b T
Thumb, 16-bit LDRH c 0 to 62 d T
Thumb, 16-bit LDRB c 0 to 31 T
Thumb, 16-bit LDR, base register is SP e 0 to 1020 b T

Notes about the Architectures column

Entries in the Architectures column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

5E

The ARMv5TE, ARMv6*, and ARMv7 architectures.

T2

The ARMv6T2 and above architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

LDR (register-relative) in Thumb

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb LDR instruction.

Doubleword register restrictions

For 32-bit Thumb instructions, you must not specify SP or PC for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register.

  • Rt must not be LR.

  • ARM strongly recommends that you do not use R12 for Rt.

  • Rt2 must be R(t + 1).

Use of PC

You can use PC for Rt in word instructions. Other uses of PC are not permitted in these instructions.

Use of SP

In ARM code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word ARM instructions but this is deprecated in ARMv6T2 and above.

In Thumb code, you can use SP for Rt in word instructions only. All other use of SP for Rt in these instructions are not permitted in Thumb code.

a 

For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

b 

Must be a multiple of 4.

c 

Rt and base register must be in the range R0-R7.

d 

Must be a multiple of 2.

e 

Rt must be in the range R0-R7.

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