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Home > ARM and Thumb Instructions > MIA, MIAPH, and MIAxy |

Multiply with Internal Accumulate, Multiply with Internal Accumulate, Packed Halfwords.

`MIA`

{

}
`cond`

, `Acc`

,
`Rn`

`Rm`

`MIAPH`

{

}
`cond`

, `Acc`

,
`Rn`

`Rm`

`MIA`

<

><`x`

>{`y`

}
`cond`

, `Acc`

,
`Rn`

`Rm`

where:

`cond`

is an optional condition code.

`Acc`

is the internal accumulator. The standard name is acc

`x`

, where`x`

is an integer in the range 0 to`n`

. The value of`n`

depends on the processor. It is 0 in current processors.`Rn, Rm`

are the ARM registers holding the values to be multiplied.

`Rn`

and`Rm`

must not be PC.- <
`x`

><`y`

> is one of:

`BB`

,`BT`

,`TB`

,`TT`

.

These instructions multiply either 16-bit or 32-bit signed integers, adding the result to a 40-bit accumulator.

The `MIA`

instruction multiplies
the signed integers from `Rn`

and `Rm`

,
and adds the result to the 40-bit value in `Acc`

.

The `MIAPH`

instruction multiplies
the signed integers from the bottom halves of `Rn`

and `Rm`

, multiplies
the signed integers from the upper halves of `Rn`

and `Rm`

,
and adds the two 32-bit results to the 40-bit value in `Acc`

.

The `MIAxy`

instruction multiplies
the signed integer from the selected half of `Rs`

by
the signed integer from the selected half of `Rm`

,
and adds the 32-bit result to the 40-bit value in `Acc`

. `<`

== B means
use the bottom half (bits [15:0]) of `x`

>`Rn`

, `<`

== T means
use the top half (bits [31:16]) of `x`

>`Rn`

. `<`

== B means
use the bottom half (bits [15:0]) of `y`

>`Rm`

, `<`

== T means
use the top half (bits [31:16]) of `y`

>`Rm`

.

These instructions do not change the flags.

These ARM coprocessor 0 instructions are only available in XScale processors.

There are no Thumb versions of these instructions.

MIA acc0,r5,r0 MIALE acc0,r1,r9 MIAPH acc0,r0,r7 MIAPHNE acc0,r11,r10 MIABB acc0,r8,r9 MIABT acc0,r8,r8 MIATB acc0,r5,r3 MIATT acc0,r0,r6 MIABTGT acc0,r2,r5