11.57 MOV

Move.

Syntax

MOV{S}{cond} Rd, Operand2

MOV{cond} Rd, #imm16

where:

S

is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Operand2

is a flexible second operand.

imm16

is any value in the range 0-65535.

Operation

The MOV instruction copies the value of Operand2 into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings.

Use of PC and SP in 32-bit Thumb encodings

You cannot use PC (R15) for Rd, or in Operand2, in 32-bit Thumb MOV instructions. With the following exceptions, you cannot use SP (R13) for Rd, or in Operand2:

  • MOV{cond}.W Rd, SP, where Rd is not SP.

  • MOV{cond}.W SP, Rm, where Rm is not SP.

Use of PC and SP in 16-bit Thumb encodings

You can use PC or SP in 16-bit Thumb MOV{cond} Rd, Rm instructions but these instructions in which both Rd and Rm are SP or PC are deprecated in ARMv6T2 and above.

You cannot use PC or SP in any other MOV{S} 16-bit Thumb instructions.

Use of PC and SP in ARM MOV

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

In instructions without register-controlled shift, the use of PC is deprecated except for the following cases:

  • MOVS PC, LR.

  • MOV PC, Rm when Rm is not PC or SP.

  • MOV Rd, PC when Rd is not PC or SP.

You can use SP for Rd or Rm. But this is deprecated except for the following cases:

  • MOV SP, Rm when Rm is not PC or SP.

  • MOV Rd, SP when Rd is not PC or SP.

Note:

  • You cannot use PC for Rd in MOV Rd, #imm16 if the #imm16 value is not a permitted Operand2 value. You can use PC in forms with Operand2 without register-controlled shift.

  • The deprecation of PC and SP in ARM instructions only applies to ARMv6T2 and above.

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

Condition flags

If S is specified, the instruction:

  • Updates the N and Z flags according to the result.

  • Can update the C flag during the calculation of Operand2.

  • Does not affect the V flag.

16-bit instructions

The following forms of this instruction are available in Thumb code, and are 16-bit instructions:

MOVS Rd, #imm

Rd must be a Lo register. imm range 0-255. This form can only be used outside an IT block.

MOV{cond} Rd, #imm

Rd must be a Lo register. imm range 0-255. This form can only be used inside an IT block.

MOVS Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used outside an IT block.

MOV{cond} Rd, Rm

In architectures before ARMv6, either Rd or Rm, or both, must be a Hi register. In ARMv6 and above, this restriction does not apply.

Architectures

The #imm16 form of the ARM instruction is available in ARMv6T2 and above. The other forms of the ARM instruction are available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

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