11.67 MUL

Multiply with signed or unsigned 32-bit operands, giving the least significant 32 bits of the result.

Syntax

MUL{S}{cond} {Rd}, Rn, Rm

where:

cond

is an optional condition code.

S

is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.

Rd

is the destination register.

Rn, Rm

are registers holding the values to be multiplied.

Operation

The MUL instruction multiplies the values from Rn and Rm, and places the least significant 32 bits of the result in Rd.

Register restrictions

Rn must be different from Rd in architectures before ARMv6.

You cannot use PC for any register.

You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

If S is specified, the MUL instruction:

  • Updates the N and Z flags according to the result.

  • Corrupts the C and V flag in ARMv4.

  • Does not affect the C or V flag in ARMv5T and above.

16-bit instructions

The following forms of the MUL instruction are available in Thumb code, and are 16-bit instructions:

MULS Rd, Rn, Rd

Rd and Rn must both be Lo registers. This form can only be used outside an IT block.

MUL{cond} Rd, Rn, Rd

Rd and Rn must both be Lo registers. This form can only be used inside an IT block.

Architectures

This ARM instruction is available in all versions of the ARM architecture.

MUL is available in a 32-bit encoding in Thumb in ARMv6T2 and above. MULS is not available in a 32-bit encoding in Thumb.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

Examples

    MUL     r10, r2, r5
    MULS    r0, r2, r2
    MULLT   r2, r3, r2
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