11.68 MVN

Move Not.

Syntax

MVN{S}{cond} Rd, Operand2

where:

S

is an optional suffix. If S is specified, the condition flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Operand2

is a flexible second operand.

Operation

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings.

Use of PC and SP in 32-bit Thumb MVN

You cannot use PC (R15) for Rd, or in Operand2, in 32-bit Thumb MVN instructions. You cannot use SP (R13) for Rd, or in Operand2.

Use of PC and SP in 16-bit Thumb instructions

You cannot use PC or SP in any MVN{S} 16-bit Thumb instructions.

Use of PC and SP in ARM MVN

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

In instructions without register-controlled shift, use of PC is deprecated.

You can use SP for Rd or Rm, but this is deprecated.

Note:

The deprecation of PC and SP in ARM instructions only applies to ARMv6T2 and above.

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

Condition flags

If S is specified, the instruction:

  • Updates the N and Z flags according to the result.

  • Can update the C flag during the calculation of Operand2.

  • Does not affect the V flag.

16-bit instructions

The following forms of this instruction are available in Thumb code, and are 16-bit instructions:

MVNS Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used outside an IT block.

MVN{cond} Rd, Rm

Rd and Rm must both be Lo registers. This form can only be used inside an IT block.

Architectures

This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above.

This 16-bit Thumb instruction is available in all T variants of the ARM architecture.

Correct example

    MVNNE   r11, #0xF000000B ; ARM only. This immediate value is not available in Thumb.

Incorrect example

    MVN     pc,r3,ASR r0     ; PC not permitted with register-controlled shift
Non-ConfidentialPDF file icon PDF versionARM DUI0473M
Copyright © 2010-2016 ARM Limited or its affiliates. All rights reserved.