11.73 PKHBT and PKHTB

Halfword Packing instructions that combine a halfword from one register with a halfword from another register. One of the operands can be shifted before extraction of the halfword.

Syntax

PKHBT{cond} {Rd}, Rn, Rm{, LSL #leftshift}

PKHTB{cond} {Rd}, Rn, Rm{, ASR #rightshift}

where:

PKHBT

Combines bits[15:0] of Rn with bits[31:16] of the shifted value from Rm.

PKHTB

Combines bits[31:16] of Rn with bits[15:0] of the shifted value from Rm.

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the first operand.

Rm

is the register holding the first operand.

leftshift

is in the range 0 to 31.

rightshift

is in the range 1 to 32.

Register restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

These instructions do not change the flags.

Architectures

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit versions of these instructions in Thumb.

Correct examples

    PKHBT   r0, r3, r5          ; combine the bottom halfword of R3 
                                ; with the top halfword of R5
    PKHBT   r0, r3, r5, LSL #16 ; combine the bottom halfword of R3
                                ; with the bottom halfword of R5
    PKHTB   r0, r3, r5, ASR #16 ; combine the top halfword of R3  
                                ; with the top halfword of R5

You can also scale the second operand by using different values of shift.

Incorrect example

    PKHBTEQ r4, r5, r1, ASR #8  ; ASR not permitted with PKHBT
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