11.114 SMLAL

Signed Long Multiply, with optional Accumulate, with 32-bit operands, and 64-bit result and accumulator.

Syntax

SMLAL{S}{cond} RdLo, RdHi, Rn, Rm

where:

S

is an optional suffix available in ARM state only. If S is specified, the condition flags are updated on the result of the operation.

cond

is an optional condition code.

RdLo, RdHi

are the destination registers. They also hold the accumulating value. RdLo and RdHi must be different registers

Rn, Rm

are ARM registers holding the operands.

Operation

The SMLAL instruction interprets the values from Rn and Rm as two’s complement signed integers. It multiplies these integers, and adds the 64-bit result to the 64-bit signed integer contained in RdHi and RdLo.

Register restrictions

Rn must be different from RdLo and RdHi in architectures before ARMv6.

You cannot use PC for any register.

You can use SP in ARM instructions but this is deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

If S is specified, this instruction:

  • Updates the N and Z flags according to the result.

  • Does not affect the C or V flags.

Architectures

This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above.

There is no 16-bit version of this instruction in Thumb.

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