11.136 STR (immediate offset)

Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate offset.

Syntax

STR{type}{cond} Rt, [Rn {, #offset}] ; immediate offset

STR{type}{cond} Rt, [Rn, #offset]! ; pre-indexed

STR{type}{cond} Rt, [Rn], #offset ; post-indexed

STRD{cond} Rt, Rt2, [Rn {, #offset}] ; immediate offset, doubleword

STRD{cond} Rt, Rt2, [Rn, #offset]! ; pre-indexed, doubleword

STRD{cond} Rt, Rt2, [Rn], #offset ; post-indexed, doubleword

where:

type

can be any one of:

B

Byte.

H

Halfword.

-

omitted, for Word.

cond

is an optional condition code.

Rt

is the register to store.

Rn

is the register on which the memory address is based.

offset

is an offset. If offset is omitted, the address is the contents of Rn.

Rt2

is the additional register to store for doubleword operations.

Not all options are available in every instruction set and architecture.

Offset ranges and architectures

The following table shows the ranges of offsets and availability of this instruction:

Table 11-15 Offsets and architectures, STR, word, halfword, and byte

Instruction Immediate offset Pre-indexed Post-indexed Arch.
ARM, word or byte –4095 to 4095 –4095 to 4095 –4095 to 4095 All
ARM, halfword –255 to 255 –255 to 255 –255 to 255 All
ARM, doubleword –255 to 255 –255 to 255 –255 to 255 5E
Thumb 32-bit encoding, word, halfword, or byte –255 to 4095 –255 to 255 –255 to 255 T2
Thumb 32-bit encoding, doubleword –1020 to 1020 a –1020 to 1020 a –1020 to 1020 a T2
Thumb 16-bit encoding, word b 0 to 124 a Not available Not available T
Thumb 16-bit encoding, halfword b 0 to 62 d Not available Not available T
Thumb 16-bit encoding, byte b 0 to 31 Not available Not available T
Thumb 16-bit encoding, word, Rn is SP c 0 to 1020 a Not available Not available T

Notes about the Architecture column

Entries in the Architecture column indicate that the instructions are available as follows:

All

All versions of the ARM architecture.

5E

The ARMv5TE, ARMv6*, and ARMv7 architectures.

T2

The ARMv6T2 and above architectures.

T

The ARMv4T, ARMv5T*, ARMv6*, and ARMv7 architectures.

Register restrictions

Rn must be different from Rt in the pre-index and post-index forms.

Doubleword register restrictions

Rn must be different from Rt2 in the pre-index and post-index forms.

For Thumb instructions, you must not specify SP or PC for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register.

  • Rt must not be LR.

  • ARM strongly recommends that you do not use R12 for Rt.

  • Rt2 must be R(t + 1).

Use of PC

In ARM instructions you can use PC for Rt in STR word instructions and PC for Rn in STR instructions with immediate offset syntax (that is the forms that do not writeback to the Rn). However, this is deprecated in ARMv6T2 and above.

Other uses of PC are not permitted in these ARM instructions.

In Thumb code, using PC in STR instructions is not permitted.

Use of SP

You can use SP for Rn.

In ARM code, you can use SP for Rt in word instructions. You can use SP for Rt in non-word instructions in ARM code but this is deprecated in ARMv6T2 and above.

In Thumb code, you can use SP for Rt in word instructions only. All other use of SP for Rt in this instruction is not permitted in Thumb code.

Example

    STR     r2,[r9,#consta-struc]   ; consta-struc is an expression
                                    ; evaluating to a constant in 
                                    ; the range 0-4095.
a 

Must be divisible by 4.

b 

Rt and Rn must be in the range R0-R7.

c 

Rt must be in the range R0-R7.

d 

Must be divisible by 2.

Non-ConfidentialPDF file icon PDF versionARM DUI0473M
Copyright © 2010-2016 ARM Limited or its affiliates. All rights reserved.