12.15 VBIC (register)

Vector Bit Clear.

Syntax

VBIC{cond}{.datatype} {Qd}, Qn, Qm

VBIC{cond}{.datatype} {Dd}, Dn, Dm

where:

cond

is an optional condition code.

datatype

is an optional data type. The assembler ignores datatype.

Qd, Qn, Qm

specifies the destination register, the first operand register, and the second operand register, for a quadword operation.

Dd, Dn, Dm

specifies the destination register, the first operand register, and the second operand register, for a doubleword operation.

Operation

VBIC performs a bitwise logical AND complement between two registers, and places the result in the destination register.

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