12.16 VBIF

Vector Bitwise Insert if False.

Syntax

VBIF{cond}{.datatype} {Qd}, Qn, Qm

VBIF{cond}{.datatype} {Dd}, Dn, Dm

where:

cond

is an optional condition code.

datatype

is an optional datatype. The assembler ignores datatype.

Qd, Qn, Qm

specifies the destination register, the first operand register, and the second operand register, for a quadword operation.

Dd, Dn, Dm

specifies the destination register, the first operand register, and the second operand register, for a doubleword operation.

Operation

VBIF inserts each bit from the first operand into the destination if the corresponding bit of the second operand is 0, otherwise it leaves the destination bit unchanged.

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