12.29 VCLT (register)

Vector Compare Less Than.

Syntax

VCLT{cond}.datatype {Qd}, Qn, Qm

VCLT{cond}.datatype {Dd}, Dn, Dm

where:

cond

is an optional condition code.

datatype

must be one of S8, S16, S32, U8, U16, U32, or F32.

The result datatype is:

  • I32 for operand datatypes S32, U32, or F32.

  • I16 for operand datatypes S16 or U16.

  • I8 for operand datatypes S8 or U8.

Qd, Qn, Qm

specifies the destination register, the first operand register, and the second operand register, for a quadword operation.

Dd, Dn, Dm

specifies the destination register, the first operand register, and the second operand register, for a doubleword operation.

Operation

VCLT takes the value of each element in a vector, and compares it with the value of the corresponding element of a second vector. If the condition is true, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

Note:

On disassembly, this pseudo-instruction is disassembled to the corresponding VCGT instruction, with the operands reversed.

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