14.4 Wireless MMX load and store instructions

Load and store a byte, halfword, word, or doubleword to and from Wireless MMX coprocessor registers.

Syntax

op<type>{cond} wRd, [Rn, #{-}offset]{!}

op<type>{cond} wRd, [Rn] {, #{-}offset}

opW{cond} wRd, label

opW wCd, [Rn, #{-}offset]{!}

opW wCd, [Rn] {, #{-}offset}

opD {cond} wRd,label

opD wRd, [Rn, {-}Rm {, LSL #imm4}]{!} ; MMX2 only

opD wRd, [Rn], {-}Rm {, LSL #imm4} ; MMX2 only

where:

op

can be either:

WLDR

Load Wireless MMX Register.

WSTR

Store Wireless MMX Register.

<type>

can be any one of:

B

Byte.

H

Halfword.

W

Word.

D

Doubleword.

cond

is an optional condition code.

wRd

is the Wireless MMX SIMD data register to load or save.

wCd

is the Wireless MMX Status and Control register to load or save.

Rn

is the register on which the memory address is based.

offset

is an immediate offset. If offset is omitted, the instruction is a zero offset instruction.

!

is an optional suffix. If ! is present, the instruction is a pre-indexed instruction.

label

is a PC-relative expression.

label must be within ± 1020 bytes of the current instruction.

Rm

is a register containing a value to be used as the offset. Rm must not be PC.

imm4

contains the number of bits to shift Rm left, in the range 0-15.

Loading constants into SIMD registers

The assembler also supports the WLDRW and WLDRD literal load pseudo-instructions, for example:

    WLDRW wr0, =0x114

Be aware that:

  • The assembler cannot load byte and halfword literals. These produce a downgradable error. If downgraded, the instruction is converted to a WLDRW and a 32-bit literal is generated. This is the same as a byte literal load, but uses a 32-bit word instead.

  • If the literal to be loaded is zero, and the destination is a SIMD Data register, the assembler converts the instruction to a WZERO.

  • Doubleword loads must be 8-byte aligned.

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