ARM® Compiler armasm User Guide

Version 5.06


Table of Contents

Preface
About this book
Using this book
Glossary
Typographic conventions
Feedback
Other information
1 Overview of the Assembler
1.1 About the ARM Compiler toolchain assemblers
1.2 Key features of the assembler
1.3 How the assembler works
1.4 Directives that can be omitted in pass 2 of the assembler
2 Overview of the ARM Architecture
2.1 About the ARM architecture
2.2 ARM, Thumb, and ThumbEE instruction sets
2.3 Changing between ARM, Thumb, and ThumbEE state
2.4 Processor modes, and privileged and unprivileged software execution
2.5 Processor modes in ARMv6-M and ARMv7-M
2.6 NEON technology
2.7 VFP hardware
2.8 ARM registers
2.9 General-purpose registers
2.10 Register accesses
2.11 Predeclared core register names
2.12 Predeclared extension register names
2.13 Predeclared XScale register names
2.14 Predeclared coprocessor names
2.15 Program Counter
2.16 Application Program Status Register
2.17 The Q flag
2.18 Current Program Status Register
2.19 Saved Program Status Registers
2.20 ARM and Thumb instruction set overview
2.21 Access to the inline barrel shifter
3 Structure of Assembly Language Modules
3.1 Syntax of source lines in assembly language
3.2 Literals
3.3 ELF sections and the AREA directive
3.4 An example ARM assembly language module
4 Writing ARM Assembly Language
4.1 About the Unified Assembler Language
4.2 Register usage in subroutine calls
4.3 Load immediate values
4.4 Load immediate values using MOV and MVN
4.5 Load immediate values using MOV32
4.6 Load immediate values using LDR Rd, =const
4.7 Literal pools
4.8 Load addresses into registers
4.9 Load addresses to a register using ADR
4.10 Load addresses to a register using ADRL
4.11 Load addresses to a register using LDR Rd, =label
4.12 Other ways to load and store registers
4.13 Load and store multiple register instructions
4.14 Load and store multiple register instructions in ARM and Thumb
4.15 Stack implementation using LDM and STM
4.16 Stack operations for nested subroutines
4.17 Block copy with LDM and STM
4.18 Memory accesses
4.19 The Read-Modify-Write operation
4.20 Optional hash with immediate constants
4.21 Use of macros
4.22 Test-and-branch macro example
4.23 Unsigned integer division macro example
4.24 Instruction and directive relocations
4.25 Symbol versions
4.26 Frame directives
4.27 Exception tables and Unwind tables
4.28 Assembly language changes after RVCT v2.1
5 Condition Codes
5.1 Conditional instructions
5.2 Conditional execution in ARM state
5.3 Conditional execution in Thumb state
5.4 Updates to the condition flags
5.5 Condition code suffixes and related flags
5.6 Comparison of condition code meanings in integer and floating-point code
5.7 Benefits of using conditional execution
5.8 Example showing the benefits of using conditional instructions
5.9 Optimization for execution speed
6 Using the Assembler
6.1 armasm command-line syntax
6.2 Specify command-line options with an environment variable
6.3 Using stdin to input source code to the assembler
6.4 Built-in variables and constants
6.5 Identifying versions of armasm in source code
6.6 Diagnostic messages
6.7 Interlocks diagnostics
6.8 Automatic IT block generation
6.9 Thumb branch target alignment
6.10 Thumb code size diagnostics
6.11 ARM and Thumb instruction portability diagnostics
6.12 Instruction width diagnostics
6.13 Two pass assembler diagnostics
6.14 Conditional assembly
6.15 Using the C preprocessor
6.16 Address alignment
6.17 Instruction width selection in Thumb
7 Symbols, Literals, Expressions, and Operators
7.1 Symbol naming rules
7.2 Variables
7.3 Numeric constants
7.4 Assembly time substitution of variables
7.5 Register-relative and PC-relative expressions
7.6 Labels
7.7 Labels for PC-relative addresses
7.8 Labels for register-relative addresses
7.9 Labels for absolute addresses
7.10 Numeric local labels
7.11 Syntax of numeric local labels
7.12 String expressions
7.13 String literals
7.14 Numeric expressions
7.15 Syntax of numeric literals
7.16 Syntax of floating-point literals
7.17 Logical expressions
7.18 Logical literals
7.19 Unary operators
7.20 Binary operators
7.21 Multiplicative operators
7.22 String manipulation operators
7.23 Shift operators
7.24 Addition, subtraction, and logical operators
7.25 Relational operators
7.26 Boolean operators
7.27 Operator precedence
7.28 Difference between operator precedence in assembly language and C
8 NEON Programming
8.1 Architecture support for NEON
8.2 Half-precision extension for NEON
8.3 Fused Multiply-Add extension for NEON
8.4 Extension register bank mapping in NEON
8.5 NEON views of the extension register bank
8.6 Load values to NEON registers
8.7 Conditional execution of NEON instructions
8.8 Floating-point exceptions in NEON
8.9 NEON data types
8.10 Extended notation extension for NEON
8.11 NEON vectors
8.12 Normal, long, wide, and narrow NEON operation
8.13 Saturating NEON instructions
8.14 NEON scalars
8.15 Polynomial arithmetic over {0,1}
8.16 NEON system registers
8.17 Flush-to-zero mode in NEON
8.18 NEON operations not affected by flush-to-zero mode
8.19 When to use flush-to-zero mode in NEON
8.20 The effects of using flush-to-zero mode in NEON
9 VFP Programming
9.1 Architecture support for VFP
9.2 Half-precision extension for VFP
9.3 Fused Multiply-Add extension for VFP
9.4 Extension register bank mapping in VFP
9.5 VFP views of the extension register bank
9.6 Load values to VFP registers
9.7 Conditional execution of VFP instructions
9.8 Floating-point exceptions in VFP
9.9 VFP data types
9.10 Extended notation extension for VFP
9.11 VFP system registers
9.12 Flush-to-zero mode
9.13 When to use flush-to-zero mode in VFP
9.14 The effects of using flush-to-zero mode in VFP
9.15 VFP operations not affected by flush-to-zero mode
9.16 VFP vector mode
9.17 Vectors in the VFP extension register bank
9.18 VFP vector wrap-around
9.19 VFP vector stride
9.20 Restriction on vector length
9.21 Control of scalar, vector, and mixed operations
9.22 Overview of VFP directives and vector notation
9.23 Pre-UAL VFP syntax and mnemonics
9.24 Vector notation
9.25 VFPASSERT SCALAR
9.26 VFPASSERT VECTOR
10 Assembler Command-line Options
10.1 --16
10.2 --32
10.3 --apcs=qualifier…qualifier
10.4 --arm
10.5 --arm_only
10.6 --bi
10.7 --bigend
10.8 --brief_diagnostics, --no_brief_diagnostics
10.9 --checkreglist
10.10 --comment_section, --no_comment_section
10.11 --compatible=name
10.12 --cpreproc
10.13 --cpreproc_opts=option[,option,…]
10.14 --cpu=list
10.15 --cpu=name
10.16 --debug
10.17 --depend=dependfile
10.18 --depend_format=string
10.19 --diag_error=tag[,tag,…]
10.20 --diag_remark=tag[,tag,…]
10.21 --diag_style={arm|ide|gnu}
10.22 --diag_suppress=tag[,tag,…]
10.23 --diag_warning=tag[,tag,…]
10.24 --dllexport_all
10.25 --dwarf2
10.26 --dwarf3
10.27 --errors=errorfile
10.28 --execstack, --no_execstack
10.29 --execute_only
10.30 --exceptions, --no_exceptions
10.31 --exceptions_unwind, --no_exceptions_unwind
10.32 --fpmode=model
10.33 --fpu=list
10.34 --fpu=name
10.35 -g
10.36 --help
10.37 -idir[,dir, …]
10.38 --keep
10.39 --length=n
10.40 --li
10.41 --library_type=lib
10.42 --list=file
10.43 --list=
10.44 --littleend
10.45 -m
10.46 --maxcache=n
10.47 --md
10.48 --no_code_gen
10.49 --no_esc
10.50 --no_hide_all
10.51 --no_regs
10.52 --no_terse
10.53 --no_warn
10.54 -o filename
10.55 --pd
10.56 --predefine "directive"
10.57 --reduce_paths, --no_reduce_paths
10.58 --regnames
10.59 --report-if-not-wysiwyg
10.60 --show_cmdline
10.61 --split_ldm
10.62 --thumb
10.63 --thumbx
10.64 --unaligned_access, --no_unaligned_access
10.65 --unsafe
10.66 --untyped_local_labels
10.67 --version_number
10.68 --via=filename
10.69 --vsn
10.70 --width=n
10.71 --xref
11 ARM and Thumb Instructions
11.1 ARM and Thumb instruction summary
11.2 Instruction width specifiers
11.3 Flexible second operand (Operand2)
11.4 Syntax of Operand2 as a constant
11.5 Syntax of Operand2 as a register with optional shift
11.6 Shift operations
11.7 Saturating instructions
11.8 Condition code suffixes
11.9 ADC
11.10 ADD
11.11 ADR (PC-relative)
11.12 ADR (register-relative)
11.13 ADRL pseudo-instruction
11.14 AND
11.15 ASR
11.16 B
11.17 BFC
11.18 BFI
11.19 BIC
11.20 BKPT
11.21 BL
11.22 BLX
11.23 BX
11.24 BXJ
11.25 CBZ and CBNZ
11.26 CDP and CDP2
11.27 CLREX
11.28 CLZ
11.29 CMP and CMN
11.30 CPS
11.31 CPY pseudo-instruction
11.32 DBG
11.33 DMB
11.34 DSB
11.35 EOR
11.36 ERET
11.37 HVC
11.38 ISB
11.39 IT
11.40 LDC and LDC2
11.41 LDM
11.42 LDR (immediate offset)
11.43 LDR (PC-relative)
11.44 LDR (register offset)
11.45 LDR (register-relative)
11.46 LDR pseudo-instruction
11.47 LDR, unprivileged
11.48 LDREX
11.49 LSL
11.50 LSR
11.51 MAR
11.52 MCR and MCR2
11.53 MCRR and MCRR2
11.54 MIA, MIAPH, and MIAxy
11.55 MLA
11.56 MLS
11.57 MOV
11.58 MOV32 pseudo-instruction
11.59 MOVT
11.60 MRA
11.61 MRC and MRC2
11.62 MRRC and MRRC2
11.63 MRS (PSR to general-purpose register)
11.64 MRS (system coprocessor register to ARM register)
11.65 MSR (ARM register to system coprocessor register)
11.66 MSR (general-purpose register to PSR)
11.67 MUL
11.68 MVN
11.69 NEG pseudo-instruction
11.70 NOP
11.71 ORN (Thumb only)
11.72 ORR
11.73 PKHBT and PKHTB
11.74 PLD, PLDW, and PLI
11.75 POP
11.76 PUSH
11.77 QADD
11.78 QADD8
11.79 QADD16
11.80 QASX
11.81 QDADD
11.82 QDSUB
11.83 QSAX
11.84 QSUB
11.85 QSUB8
11.86 QSUB16
11.87 RBIT
11.88 REV
11.89 REV16
11.90 REVSH
11.91 RFE
11.92 ROR
11.93 RRX
11.94 RSB
11.95 RSC
11.96 SADD8
11.97 SADD16
11.98 SASX
11.99 SBC
11.100 SBFX
11.101 SDIV
11.102 SEL
11.103 SETEND
11.104 SEV
11.105 SHADD8
11.106 SHADD16
11.107 SHASX
11.108 SHSAX
11.109 SHSUB8
11.110 SHSUB16
11.111 SMC
11.112 SMLAxy
11.113 SMLAD
11.114 SMLAL
11.115 SMLALD
11.116 SMLALxy
11.117 SMLAWy
11.118 SMLSD
11.119 SMLSLD
11.120 SMMLA
11.121 SMMLS
11.122 SMMUL
11.123 SMUAD
11.124 SMULxy
11.125 SMULL
11.126 SMULWy
11.127 SMUSD
11.128 SRS
11.129 SSAT
11.130 SSAT16
11.131 SSAX
11.132 SSUB8
11.133 SSUB16
11.134 STC and STC2
11.135 STM
11.136 STR (immediate offset)
11.137 STR (register offset)
11.138 STR, unprivileged
11.139 STREX
11.140 SUB
11.141 SUBS pc, lr
11.142 SVC
11.143 SWP and SWPB
11.144 SXTAB
11.145 SXTAB16
11.146 SXTAH
11.147 SXTB
11.148 SXTB16
11.149 SXTH
11.150 SYS
11.151 TBB and TBH
11.152 TEQ
11.153 TST
11.154 UADD8
11.155 UADD16
11.156 UASX
11.157 UBFX
11.158 UDIV
11.159 UHADD8
11.160 UHADD16
11.161 UHASX
11.162 UHSAX
11.163 UHSUB8
11.164 UHSUB16
11.165 UMAAL
11.166 UMLAL
11.167 UMULL
11.168 UND pseudo-instruction
11.169 UQADD8
11.170 UQADD16
11.171 UQASX
11.172 UQSAX
11.173 UQSUB8
11.174 UQSUB16
11.175 USAD8
11.176 USADA8
11.177 USAT
11.178 USAT16
11.179 USAX
11.180 USUB8
11.181 USUB16
11.182 UXTAB
11.183 UXTAB16
11.184 UXTAH
11.185 UXTB
11.186 UXTB16
11.187 UXTH
11.188 WFE
11.189 WFI
11.190 YIELD
12 NEON Instructions
12.1 Summary of NEON instructions
12.2 Summary of shared NEON and VFP instructions
12.3 Interleaving provided by load and store element and structure instructions
12.4 Alignment restrictions in load and store element and structure instructions
12.5 VABA and VABAL
12.6 VABD and VABDL
12.7 VABS
12.8 VACLE, VACLT, VACGE and VACGT
12.9 VADD
12.10 VADDHN
12.11 VADDL and VADDW
12.12 VAND (immediate)
12.13 VAND (register)
12.14 VBIC (immediate)
12.15 VBIC (register)
12.16 VBIF
12.17 VBIT
12.18 VBSL
12.19 VCEQ (immediate #0)
12.20 VCEQ (register)
12.21 VCGE (immediate #0)
12.22 VCGE (register)
12.23 VCGT (immediate #0)
12.24 VCGT (register)
12.25 VCLE (immediate #0)
12.26 VCLE (register)
12.27 VCLS
12.28 VCLT (immediate #0)
12.29 VCLT (register)
12.30 VCLZ
12.31 VCNT
12.32 VCVT (between fixed-point or integer, and floating-point)
12.33 VCVT (between half-precision and single-precision floating-point)
12.34 VDUP
12.35 VEOR
12.36 VEXT
12.37 VFMA, VFMS
12.38 VHADD
12.39 VHSUB
12.40 VLDn (single n-element structure to one lane)
12.41 VLDn (single n-element structure to all lanes)
12.42 VLDn (multiple n-element structures)
12.43 VLDM
12.44 VLDR
12.45 VLDR (post-increment and pre-decrement)
12.46 VLDR pseudo-instruction
12.47 VMAX and VMIN
12.48 VMLA
12.49 VMLA (by scalar)
12.50 VMLAL (by scalar)
12.51 VMLAL
12.52 VMLS (by scalar)
12.53 VMLS
12.54 VMLSL
12.55 VMLSL (by scalar)
12.56 VMOV (floating-point)
12.57 VMOV (immediate)
12.58 VMOV (register)
12.59 VMOV (between two ARM registers and a 64-bit extension register)
12.60 VMOV (between an ARM register and a NEON scalar)
12.61 VMOVL
12.62 VMOVN
12.63 VMOV2
12.64 VMRS
12.65 VMSR
12.66 VMUL
12.67 VMUL (by scalar)
12.68 VMULL
12.69 VMULL (by scalar)
12.70 VMVN (register)
12.71 VMVN (immediate)
12.72 VNEG
12.73 VORN (register)
12.74 VORN (immediate)
12.75 VORR (register)
12.76 VORR (immediate)
12.77 VPADAL
12.78 VPADD
12.79 VPADDL
12.80 VPMAX and VPMIN
12.81 VPOP
12.82 VPUSH
12.83 VQABS
12.84 VQADD
12.85 VQDMLAL and VQDMLSL (by vector or by scalar)
12.86 VQDMULH (by vector or by scalar)
12.87 VQDMULL (by vector or by scalar)
12.88 VQMOVN and VQMOVUN
12.89 VQNEG
12.90 VQRDMULH (by vector or by scalar)
12.91 VQRSHL (by signed variable)
12.92 VQRSHRN and VQRSHRUN (by immediate)
12.93 VQSHL (by signed variable)
12.94 VQSHL and VQSHLU (by immediate)
12.95 VQSHRN and VQSHRUN (by immediate)
12.96 VQSUB
12.97 VRADDHN
12.98 VRECPE
12.99 VRECPS
12.100 VREV16, VREV32, and VREV64
12.101 VRHADD
12.102 VRSHL (by signed variable)
12.103 VRSHR (by immediate)
12.104 VRSHRN (by immediate)
12.105 VRSQRTE
12.106 VRSQRTS
12.107 VRSRA (by immediate)
12.108 VRSUBHN
12.109 VSHL (by immediate)
12.110 VSHL (by signed variable)
12.111 VSHLL (by immediate)
12.112 VSHR (by immediate)
12.113 VSHRN (by immediate)
12.114 VSLI
12.115 VSRA (by immediate)
12.116 VSRI
12.117 VSTM
12.118 VSTn (multiple n-element structures)
12.119 VSTn (single n-element structure to one lane)
12.120 VSTR
12.121 VSTR (post-increment and pre-decrement)
12.122 VSUB
12.123 VSUBHN
12.124 VSUBL and VSUBW
12.125 VSWP
12.126 VTBL and VTBX
12.127 VTRN
12.128 VTST
12.129 VUZP
12.130 VZIP
13 VFP Instructions
13.1 Summary of VFP instructions
13.2 VABS (floating-point)
13.3 VADD (floating-point)
13.4 VCMP, VCMPE
13.5 VCVT (between single-precision and double-precision)
13.6 VCVT (between floating-point and integer)
13.7 VCVT (between floating-point and fixed-point)
13.8 VCVTB, VCVTT (half-precision extension)
13.9 VDIV
13.10 VFMA, VFMS, VFNMA, VFNMS (floating-point)
13.11 VLDM (floating-point)
13.12 VLDR (floating-point)
13.13 VLDR (post-increment and pre-decrement, floating-point)
13.14 VLDR pseudo-instruction
13.15 VMLA (floating-point)
13.16 VMLS (floating-point)
13.17 VMOV (floating-point)
13.18 VMOV (between one ARM register and single precision VFP)
13.19 VMOV (between two ARM registers and one or two extension registers)
13.20 VMOV (between an ARM register and half a double precision VFP register)
13.21 VMRS
13.22 VMSR
13.23 VMUL (floating-point)
13.24 VNEG (floating-point)
13.25 VNMLA (floating-point)
13.26 VNMLS (floating-point)
13.27 VNMUL (floating-point)
13.28 VPOP (floating-point)
13.29 VPUSH (floating-point)
13.30 VSQRT
13.31 VSTM (floating-point)
13.32 VSTR (floating-point)
13.33 VSTR (post-increment and pre-decrement, floating-point)
13.34 VSUB (floating-point)
14 Wireless MMX Technology Instructions
14.1 About Wireless MMX Technology instructions
14.2 WRN and WCN directives to support Wireless MMX Technology
14.3 Frame directives and Wireless MMX Technology
14.4 Wireless MMX load and store instructions
14.5 Wireless MMX Technology and XScale instructions
14.6 Wireless MMX instructions
14.7 Wireless MMX pseudo-instructions
15 Directives Reference
15.1 Alphabetical list of directives
15.2 About assembly control directives
15.3 About frame directives
15.4 ALIAS
15.5 ALIGN
15.6 AREA
15.7 ARM or CODE32
15.8 ASSERT
15.9 ATTR
15.10 CN
15.11 CODE16
15.12 COMMON
15.13 CP
15.14 DATA
15.15 DCB
15.16 DCD and DCDU
15.17 DCDO
15.18 DCFD and DCFDU
15.19 DCFS and DCFSU
15.20 DCI
15.21 DCQ and DCQU
15.22 DCW and DCWU
15.23 END
15.24 ENDFUNC or ENDP
15.25 ENTRY
15.26 EQU
15.27 EXPORT or GLOBAL
15.28 EXPORTAS
15.29 FIELD
15.30 FRAME ADDRESS
15.31 FRAME POP
15.32 FRAME PUSH
15.33 FRAME REGISTER
15.34 FRAME RESTORE
15.35 FRAME RETURN ADDRESS
15.36 FRAME SAVE
15.37 FRAME STATE REMEMBER
15.38 FRAME STATE RESTORE
15.39 FRAME UNWIND ON
15.40 FRAME UNWIND OFF
15.41 FUNCTION or PROC
15.42 GBLA, GBLL, and GBLS
15.43 GET or INCLUDE
15.44 IF, ELSE, ENDIF, and ELIF
15.45 IMPORT and EXTERN
15.46 INCBIN
15.47 INFO
15.48 KEEP
15.49 LCLA, LCLL, and LCLS
15.50 LTORG
15.51 MACRO and MEND
15.52 MAP
15.53 MEXIT
15.54 NOFP
15.55 OPT
15.56 QN, DN, and SN
15.57 RELOC
15.58 REQUIRE
15.59 REQUIRE8 and PRESERVE8
15.60 RLIST
15.61 RN
15.62 ROUT
15.63 SETA, SETL, and SETS
15.64 SPACE or FILL
15.65 THUMB
15.66 THUMBX
15.67 TTL and SUBT
15.68 WHILE and WEND
16 Via File Syntax
16.1 Overview of via files
16.2 Via file syntax rules
A Assembler Document Revisions
A.1 Revisions for armasm User Guide

List of Figures

2-1 Organization of general-purpose registers and Program Status Registers
8-1 NEON extension register bank
9-1 VFP extension register bank
9-2 VFPv2 register banks
9-3 VFPv3 register banks
11-1 ASR #3
11-2 LSR #3
11-3 LSL #3
11-4 ROR #3
11-5 RRX
12-1 De-interleaving an array of 3-element structures
12-2 Operation of doubleword VEXT for imm = 3
12-3 Example of operation of VPADAL (in this case for data type S16)
12-4 Example of operation of VPADD (in this case, for data type I16)
12-5 Example of operation of doubleword VPADDL (in this case, for data type S16)
12-6 Operation of quadword VSHL.I64 Qd, Qm, #1
12-7 Operation of quadword VSLI.64 Qd, Qm, #1
12-8 Operation of doubleword VSRI.64 Dd, Dm, #2
12-9 Operation of doubleword VTRN.8
12-10 Operation of doubleword VTRN.32

List of Tables

2-1 ARM processor modes
2-2 Predeclared core registers
2-3 Predeclared extension registers
2-4 Predeclared XScale registers
2-5 Predeclared Wireless MMX registers
2-6 Predeclared coprocessor registers
2-7 Instruction groups
4-1 Stack-oriented suffixes and equivalent addressing mode suffixes
4-2 Suffixes for load and store multiple instructions
4-3 Changes from earlier ARM assembly language
4-4 Relaxation of requirements
4-5 Differences between pre-UAL Thumb syntax and UAL syntax
5-1 Condition code suffixes and related flags
5-2 Condition codes
5-3 Conditional branches only
5-4 All instructions conditional
6-1 Built-in variables
6-2 Built-in Boolean constants
6-3 Predefined macros
6-4 {TARGET_ARCH_ARM} in relation to {TARGET_ARCH_THUMB}
6-5 Command-line options
6-6 armcc equivalent command-line options
7-1 Unary operators that return strings
7-2 Unary operators that return numeric or logical values
7-3 Multiplicative operators
7-4 String manipulation operators
7-5 Shift operators
7-6 Addition, subtraction, and logical operators
7-7 Relational operators
7-8 Boolean operators
7-9 Operator precedence in ARM assembly language
7-10 Operator precedence in C
8-1 NEON data type specifiers
8-2 NEON saturation ranges
9-1 VFP data type specifiers
9-2 Pre-UAL VFP mnemonics
9-3 Floating-point values for use with FCONST
10-1 Compatible processor or architecture combinations
10-2 Supported ARM architectures
10-3 Severity of diagnostic messages
10-4 Specifying a command-line option and an AREA directive for GNU-stack sections
11-1 Summary of ARM and Thumb instructions
11-2 Condition code suffixes
11-3 PC-relative offsets
11-4 Register-relative offsets
11-5 B instruction availability and range
11-6 BL instruction availability and range
11-7 BLX instruction availability and range
11-8 BX instruction availability and range
11-9 BXJ instruction availability and range
11-10 Offsets and architectures, LDR, word, halfword, and byte
11-11 PC-relative offsets
11-12 Options and architectures, LDR (register offsets)
11-13 Register-relative offsets
11-14 Offsets and architectures, LDR (User mode)
11-15 Offsets and architectures, STR, word, halfword, and byte
11-16 Options and architectures, STR (register offsets)
11-17 Offsets and architectures, STR (User mode)
11-18 Range and encoding of expr
12-1 Summary of NEON instructions
12-2 Summary of shared NEON and VFP instructions
12-3 Patterns for immediate value in VBIC (immediate)
12-4 Permitted combinations of parameters for VLDn (single n-element structure to one lane)
12-5 Permitted combinations of parameters for VLDn (single n-element structure to all lanes)
12-6 Permitted combinations of parameters for VLDn (multiple n-element structures)
12-7 Available immediate values in VMOV (immediate)
12-8 Available immediate values in VMVN (immediate)
12-9 Patterns for immediate value in VORR (immediate)
12-10 Available immediate ranges in VQRSHRN and VQRSHRUN (by immediate)
12-11 Available immediate ranges in VQSHL and VQSHLU (by immediate)
12-12 Available immediate ranges in VQSHRN and VQSHRUN (by immediate)
12-13 Results for out-of-range inputs in VRECPE
12-14 Results for out-of-range inputs in VRECPS
12-15 Available immediate ranges in VRSHR (by immediate)
12-16 Available immediate ranges in VRSHRN (by immediate)
12-17 Results for out-of-range inputs in VRSQRTE
12-18 Results for out-of-range inputs in VRSQRTS
12-19 Available immediate ranges in VRSRA (by immediate)
12-20 Available immediate ranges in VSHL (by immediate)
12-21 Available immediate ranges in VSHLL (by immediate)
12-22 Available immediate ranges in VSHR (by immediate)
12-23 Available immediate ranges in VSHRN (by immediate)
12-24 Available immediate ranges in VSRA (by immediate)
12-25 Permitted combinations of parameters for VSTn (multiple n-element structures)
12-26 Permitted combinations of parameters for VSTn (single n-element structure to one lane)
12-27 Operation of doubleword VUZP.8
12-28 Operation of quadword VUZP.32
12-29 Operation of doubleword VZIP.8
12-30 Operation of quadword VZIP.32
13-1 Summary of VFP instructions
14-1 Wireless MMX Technology instructions
14-2 Wireless MMX Technology pseudo-instructions
15-1 List of directives
15-2 OPT directive settings
A-1 Differences between issue L and issue M
A-2 Differences between issue K and issue L
A-3 Differences between issue J and issue K
A-4 Differences between issue I and issue J
A-5 Differences between issue H and issue I
A-6 Differences between issue G and issue H
A-7 Differences between issue F and issue G
A-8 Differences between issue E and issue F
A-9 Differences between issue D and issue E
A-10 Differences between issue C and issue D
A-11 Differences between issue B and issue C
A-12 Differences between issue A and issue B

Release Information

Document History
Issue Date Confidentiality Change
A May 2010 Non-Confidential ARM Compiler v4.1 Release
B 30 September 2010 Non-Confidential Update 1 for ARM Compiler v4.1
C 28 January 2011 Non-Confidential Update 2 for ARM Compiler v4.1 Patch 3
D 30 April 2011 Non-Confidential ARM Compiler v5.0 Release
E 29 July 2011 Non-Confidential Update 1 for ARM Compiler v5.0
F 30 September 2011 Non-Confidential ARM Compiler v5.01 Release
G 29 February 2012 Non-Confidential Document update 1 for ARM Compiler v5.01 Release
H 27 July 2012 Non-Confidential ARM Compiler v5.02 Release
I 31 January 2013 Non-Confidential ARM Compiler v5.03 Release
J 27 November 2013 Non-Confidential ARM Compiler v5.04 Release
K 10 September 2014 Non-Confidential ARM Compiler v5.05 Release
L 29 July 2015 Non-Confidential ARM Compiler v5.06 Release
M 11 November 2016 Non-Confidential Update 3 for ARM Compiler v5.06 Release

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