9.4 Extension register bank mapping in VFP

The VFP extension register bank is a collection of registers that can be accessed as either 32-bit or 64-bit registers.

The following figure shows the views of the VFP extension register bank, and the overlap between the different size registers. For example, the 64-bit register D0 is an alias for two consecutive 32-bit registers S0, S1.

Figure 9-1 VFP extension register bank
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Note:

The figure applies to a VFP implementation with 32 double precision registers. The following versions of VFP use 16 double precision registers, D0-D15.

  • VFPv2.
  • VFPv3-D16.
  • VFPv3-D16-FP16.
  • VFPv4-D16.

NEON technology uses 32 double precision registers, so if your processor implements one of the VFP versions in this list, it cannot also implement NEON technology.

The aliased views enable half-precision, single-precision, and double-precision values to coexist in different non-overlapped registers at the same time.

You can also use the same overlapped registers to store half-precision, single-precision, and double-precision values at different times.

Do not attempt to use overlapped 32-bit and 64-bit registers at the same time because it creates meaningless results.

The mapping between the registers is as follows:

  • S<2n> maps to the least significant half of D<n>.

  • S<2n+1> maps to the most significant half of D<n>.

For example, you can access the least significant half of the elements of a vector in D6 by referring to S12, and the most significant half of the elements by referring to S13.

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