13.19 VMOV (between two ARM registers and one or two extension registers)

Transfer contents between two ARM registers and either one 64-bit register or two consecutive 32-bit registers.

Syntax

VMOV{cond} Dm, Rd, Rn

VMOV{cond} Rd, Rn, Dm

VMOV{cond} Sm, Sm1, Rd, Rn

VMOV{cond} Rd, Rn, Sm, Sm1

where:

cond

is an optional condition code.

Dm

is a 64-bit extension register.

Sm

is a VFP 32-bit register.

Sm1

is the next consecutive VFP 32-bit register after Sm.

Rd, Rn

are the ARM registers. Rd and Rn must not be PC.

Operation

VMOV Dm, Rd, Rn transfers the contents of Rd into the low half of Dm, and the contents of Rn into the high half of Dm.

VMOV Rd, Rn, Dm transfers the contents of the low half of Dm into Rd, and the contents of the high half of Dm into Rn.

VMOV Rd, Rn, Sm, Sm1 transfers the contents of Sm into Rd, and the contents of Sm1 into Rn.

VMOV Sm, Sm1, Rd, Rn transfers the contents of Rd into Sm, and the contents of Rn into Sm1.

Architectures

The instructions are available in VFPv2 and above.

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