VLDn and VSTn (multiple n-element structures)

Vector Load multiple n-element structures. It loads multiple n-element structures from memory into one or more NEON registers, with de-interleaving (unless n == 1). Every element of each register is loaded.

Vector Store multiple n-element structures. It stores multiple n-element structures to memory from one or more NEON registers, with interleaving (unless n == 1). Every element of each register is stored.

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Vopn{cond}.datatype list, [Rn{@align}]{!}
Vopn{cond}.datatype list, [Rn{@align}], Rm

where:

op

must be either LD or ST.

n

must be one of 1, 2, 3, or 4.

cond

is an optional condition code.

datatype

see Table 28 for options.

list

specifies the NEON register list. See Table 28 for options.

Rn

is the ARM register containing the base address. Rn cannot be PC.

align

specifies an optional alignment. See Table 28 for options.

!

if ! is present, Rn is updated to (Rn + the number of bytes transferred by the instruction). The update occurs after all the loads or stores have taken place.

Rm

is an ARM register containing an offset from the base address. If Rm is present, Rn is updated to (Rn + Rm) after the address is used to access memory. Rm cannot be SP or PC.

Table 28. Permitted combinations of parameters

ndatatypelist [a]align [b]alignment
18, 16, 32, or 64{Dd}@648-byte
  {Dd, D(d+1)}@64 or @1288-byte or 16-byte
  {Dd, D(d+1), D(d+2)}@648-byte
  {Dd, D(d+1), D(d+2), D(d+3)}@64, @128, or @2568-byte, 16-byte, or 32-byte
28, 16, or 32{Dd, D(d+1)}@64, @1288-byte or 16-byte
  {Dd, D(d+2)}@64, @1288-byte or 16-byte
  {Dd, D(d+1), D(d+2), D(d+3)}@64, @128, or @2568-byte, 16-byte, or 32-byte
38, 16, or 32{Dd, D(d+1), D(d+2)}@648-byte
  {Dd, D(d+2), D(d+4)}@648-byte
48, 16, or 32{Dd, D(d+1), D(d+2), D(d+3)}@64, @128, or @2568-byte, 16-byte, or 32-byte
  {Dd, D(d+2), D(d+4), D(d+6)}@64, @128, or @2568-byte, 16-byte, or 32-byte

[a] Every register in the list must be in the range D0-D31.

[b] align can be omitted. In this case, standard alignment rules apply, see Alignment restrictions in load and store, element and structure instructions.


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Reference:
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