VLDn and VSTn (single n-element structure to one lane)

Vector Load single n-element structure to one lane. It loads one n-element structure from memory into one or more NEON registers. Elements of the register that are not loaded are unaltered.

Vector Store single n-element structure to one lane. It stores one n-element structure into memory from one or more NEON registers.


Vopn{cond}.datatype list, [Rn{@align}]{!}
Vopn{cond}.datatype list, [Rn{@align}], Rm



must be either LD or ST.


must be one of 1, 2, 3, or 4.


is an optional condition code.


specifies the NEON register list. See Table 26 for options.


is the ARM register containing the base address. Rn cannot be PC.


specifies an optional alignment. See Table 26 for options.


if ! is present, Rn is updated to (Rn + the number of bytes transferred by the instruction). The update occurs after all the loads or stores have taken place.


is an ARM register containing an offset from the base address. If Rm is present, Rn is updated to (Rn + Rm) after the address is used to access memory. Rm cannot be SP or PC.

Table 26. Permitted combinations of parameters

ndatatypelist [a]align [b]alignment
18{Dd[x]}-Standard only
28{Dd[x], D(d+1)[x]}@162-byte
 16{Dd[x], D(d+1)[x]}@324-byte
  {Dd[x], D(d+2)[x]}@324-byte
 32{Dd[x], D(d+1)[x]}@648-byte
  {Dd[x], D(d+2)[x]}@648-byte
38{Dd[x], D(d+1)[x], D(d+2)[x]}-Standard only
 16 or 32{Dd[x], D(d+1)[x], D(d+2)[x]}-Standard only
  {Dd[x], D(d+2)[x], D(d+4)[x]}-Standard only
48{Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]}@324-byte
 16{Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]}@648-byte
  {Dd[x], D(d+2)[x], D(d+4)[x], D(d+6)[x]}@648-byte
 32{Dd[x], D(d+1)[x], D(d+2)[x], D(d+3)[x]}@64 or @1288-byte or 16-byte
  {Dd[x], D(d+2)[x], D(d+4)[x], D(d+6)[x]}@64 or @1288-byte or 16-byte

[a] Every register in the list must be in the range D0-D31.

[b] align can be omitted. In this case, standard alignment rules apply, see Alignment restrictions in load and store, element and structure instructions.

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