VCEQ, VCGE, VCGT, VCLE, and VCLT

Vector Compare takes the value of each element in a vector, and compares it with the value of the corresponding element of a second vector, or zero. If the condition is true, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

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VCop{cond}.datatype {Qd}, Qn, Qm
VCop{cond}.datatype {Dd}, Dn, Dm
VCop{cond}.datatype {Qd}, Qn, #0
VCop{cond}.datatype {Dd}, Dn, #0

where:

op

must be one of:

EQ

Equal

GE

Greater than or Equal

GT

Greater Than

LE

Less than or Equal (only if the second operand is #0)

LT

Less Than (only if the second operand is #0).

cond

is an optional condition code.

datatype

must be one of:

  • I8, I16, I32, or F32 for EQ

  • S8, S16, S32, U8, U16, U32, or F32 for GE, GT, LE, or LT (except #0 form)

  • S8, S16, S32, or F32 for GE, GT, LE, or LT (#0 form).

The result datatype is:

  • I32 for operand datatypes I32, S32, U32, or F32

  • I16 for operand datatypes I16, S16, or U16

  • I8 for operand datatypes I8, S8, or U8.

Qd, Qn, Qm

specifies the destination register, the first operand register, and the second operand register, for a quadword operation.

Dd, Dn, Dm

specifies the destination register, the first operand register, and the second operand register, for a doubleword operation.

#0

replaces Qm or Dm for comparisons with zero.

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Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489C
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