Pseudo-instructions that load or store extension registers with post-increment and pre-decrement.
Note
There are also VLDR and VSTR instructions
without post-increment and pre-decrement.
Syntaxop{cond}{.size}Fd, [Rn], #offset; post-increment
op{cond}{.size}Fd, [Rn, #-offset]! ; pre-decrement
where:
opcan be:
VLDR- load extension register from memoryVSTR- store contents of extension register to memory.
condis an optional condition code.
sizeis an optional data size specifier. Must be 32 if
FdSregister, or 64 ifFdDregister.Fdis the extension register to be loaded or saved. For a NEON instruction, it must be a doubleword (
DdDdSdRnis the ARM register holding the base address for the transfer.
offsetis a numeric expression that must evaluate to a numeric value at assembly time. The value must be
4ifFdSregister, or8ifFdDregister.
The post-increment instruction increments the base address
in the register by the offset value, after the transfer. The pre-decrement
instruction decrements the base address in the register by the offset
value, and then performs the transfer using the new address in the
register. These pseudo-instructions assemble to VLDM or VSTM instructions.
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