ARM Compiler toolchain Assembler Reference: ADD, SUB, RSB, ADC, SBC, and RSC

ADD, SUB, RSB, ADC, SBC, and RSC

Add, Subtract, and Reverse Subtract, each with or without Carry.

Syntax

op{S}{cond} {Rd}, Rn, Operand2

op{cond} {Rd}, Rn, #imm12               ; Thumb-2 ADD and SUB only

where:

op

is one of:

ADD: Add.
ADC: Add with Carry.
SUB: Subtract.
RSB: Reverse Subtract.
SBC: Subtract with Carry.
RSC: Reverse Subtract with Carry (ARM only).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand.

imm12

is any value in the range 0-4095.

Usage

The ADD instruction adds the values in Rn and Operand2 or imm12.

The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.

The RSB (Reverse Subtract) instruction subtracts the value in Rn from the value of Operand2. This is useful because of the wide range of options for Operand2.

You can use ADC, SBC, and RSC to synthesize multiword arithmetic.

The ADC (Add with Carry) instruction adds the values in Rn and Operand2, together with the carry flag.

The SBC (Subtract with Carry) instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is clear, the result is reduced by one.

The RSC (Reverse Subtract with Carry) instruction subtracts the value in Rn from the value of Operand2. If the carry flag is clear, the result is reduced by one.

In certain circumstances, the assembler can substitute one instruction for another. Be aware of this when reading disassembly listings.

Use of PC and SP in Thumb instructions

In most of these instructions, you cannot use PC (R15) for Rd, or any operand.

The exceptions are:

you can use PC for Rn in 32-bit Thumb ADD and SUB instructions, with a constant Operand2 value in the range 0-4095, and no S suffix. These instructions are useful for generating PC-relative addresses. Bit[1] of the PC value reads as 0 in this case, so that the base address for the calculation is always word-aligned.
you can use PC in 16-bit Thumb ADD{cond} Rd, Rd, Rm instructions, where both registers cannot be PC. However, the following 16-bit Thumb instructions are deprecated in ARMv6T2 and above:
- ADD{cond} PC, SP, PC
- ADD{cond} SP, SP, PC.

In most of these instructions, you cannot use SP (R13) for Rd, or any operand. Except that:

You can use SP for Rn in ADD and SUB instructions
ADD{cond} SP, SP, SP is permitted but is deprecated in ARMv6T2 and above
ADD{S}{cond} SP, SP, Rm{,shift} and SUB{S}{cond} SP, SP, Rm{,shift} are permitted if shift is omitted or LSL #1, LSL #2, or LSL #3.

Use of PC and SP in ARM instructions

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

With the exception of ADD and SUB, use of PC for any operand, in instructions without register-controlled shift, is deprecated.

In SUB instructions without register-controlled shift, use of PC is deprecated except for the following cases:

Use of PC for Rd
Use of PC for Rn in the instruction SUB{cond} Rd, Rn, #Constant.

In ADD instructions without register-controlled shift, use of PC is deprecated except for the following cases:

Use of PC for Rd in instructions that do not add SP to a register
Use of PC for Rn and use of PC for Rm in instructions that add two registers other than SP
Use of PC for Rn in the instruction ADD{cond} Rd, Rn, #Constant.

If you use PC (R15) as Rn or Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

Execution branches to the address corresponding to the result.
If you use the S suffix, see the SUBS pc,lr instruction.

You can use SP for Rn in ADD and SUB instructions, however, ADDS PC, SP, #Constant and SUBS PC, SP, #Constant are deprecated.

You can use SP in ADD (register) and SUB (register) if Rn is SP and shift is omitted or LSL #1, LSL #2, or LSL #3.

Other uses of SP in these ARM instructions are deprecated.

Note

The deprecation of SP and PC in ARM instructions is only in ARMv6T2 and above.

Condition flags

If S is specified, these instructions update the N, Z, C and V flags according to the result.

16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

ADDS Rd, Rn, #imm: imm range 0-7. Rd and Rn must both be Lo registers.
ADDS Rd, Rn, Rm: Rd, Rn and Rm must all be Lo registers.
ADD Rd, Rd, Rm: ARMv6 and earlier: either Rd or Rm, or both, must be a Hi register. ARMv6T2 and above: this restriction does not apply.
ADDS Rd, Rd, #imm: imm range 0-255. Rd must be a Lo register.
ADCS Rd, Rd, Rm: Rd, Rn and Rm must all be Lo registers.
ADD SP, SP, #imm: imm range 0-508, word aligned.
ADD Rd, SP, #imm: imm range 0-1020, word aligned. Rd must be a Lo register.
ADD Rd, pc, #imm: imm range 0-1020, word aligned. Rd must be a Lo register. Bits[1:0] of the PC are read as 0 in this instruction.
SUBS Rd, Rn, Rm: Rd, Rn and Rm must all be Lo registers.
SUBS Rd, Rn, #imm: imm range 0-7. Rd and Rn both Lo registers.
SUBS Rd, Rd, #imm: imm range 0-255. Rd must be a Lo register.
SBCS Rd, Rd, Rm: Rd, Rn and Rm must all be Lo registers.
SUB SP, SP, #imm: imm range 0-508, word aligned.
RSBS Rd, Rn, #0: Rd and Rn both Lo registers.

Examples

    ADD     r2, r1, r3
    SUBS    r8, r6, #240        ; sets the flags on the result
    RSB     r4, r4, #1280       ; subtracts contents of R4 from 1280
    ADCHI   r11, r0, r3         ; only executed if C flag set and Z
                                ; flag clear
    RSCSLE  r0,r5,r0,LSL r4     ; conditional, flags set

Incorrect example

    RSCSLE  r0,pc,r0,LSL r4    ; PC not permitted with register
                                ; controlled shift

Multiword arithmetic examples

These two instructions add a 64-bit integer contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.

    ADDS    r4, r0, r2    ; adding the least significant words
    ADC     r5, r1, r3    ; adding the most significant words

These instructions subtract one 96-bit integer from another:

    SUBS    r3, r6, r9
    SBCS    r4, r7, r10
    SBC     r5, r8, r11

For clarity, the above examples use consecutive registers for multiword values. There is no requirement to do this. The following, for example, is perfectly valid:

    SUBS    r6, r6, r9
    SBCS    r9, r2, r1
    SBC     r2, r8, r11

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