Move to ARM Register or Registers from Coprocessor.
Depending on the coprocessor, you might be able to specify various operations in addition.
Syntax{op1cond}coproc, #opcode1,Rt,CRn,CRm{, #opcode2}
{op2cond}coproc, #opcode3,Rt,Rt2,CRm
where:
op1is either
MRCorMRC2.op2is either
MRRCorMRRC2.condis an optional condition code. In ARM code,
condMRC2orMRRC2.coprocis the name of the coprocessor the instruction is for. The standard name is
p, wherennopcode1is a 3-bit coprocessor-specific opcode.
opcode2is an optional 3-bit coprocessor-specific opcode.
opcode3is a 4-bit coprocessor-specific opcode.
Rt,Rt2are ARM destination registers.
RandtRmust not be PC.t2In
MRCandMRC2,RtAPSR_nzcv. This means that the coprocessor executes an instruction that changes the value of the condition code flags in the APSR.CRn,CRmare coprocessor registers.
The use of these instructions depends on the coprocessor. See the coprocessor documentation for details.
The MRC ARM instruction is available in all versions
of the ARM architecture.
The MRC2 ARM instruction is available in ARMv5T
and above.
The MRRC ARM instruction is available in ARMv6
and above, and E variants of ARMv5T.
The MRRC2 ARM instruction is available in ARMv6
and above.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
There are no 16-bit Thumb versions of these instructions.
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