MSR

Load an immediate value, or the contents of a general-purpose register, into specified fields of a Program Status Register (PSR).

Show/hideSyntax

MSR{cond} APSR_flags, Rm

where:

cond

is an optional condition code.

flags

specifies the APSR flags to be moved. flags can be one or more of:

nzcvq

ALU flags field mask, PSR[31:27] (User mode)

g

SIMD GE flags field mask, PSR[19:16] (User mode).

Rm

is the source register. Rm must not be PC.

Show/hideSyntax (except ARMv7-M and ARMv6-M)

You can also use the following syntax on architectures other than ARMv7 and ARMv6M.

MSR{cond} APSR_flags, #constant
MSR{cond} psr_fields, #constant
MSR{cond} psr_fields, Rm

where:

cond

is an optional condition code.

flags

specifies the APSR flags to be moved. flags can be one or more of:

nzcvq

ALU flags field mask, PSR[31:27] (User mode)

g

SIMD GE flags field mask, PSR[19:16] (User mode).

constant

is an expression evaluating to a numeric value. The value must correspond to an 8-bit pattern rotated by an even number of bits within a 32-bit word. Not available in Thumb.

Rm

is the source register. Rm must not be PC.

psr

is one of:

CPSR

for use in Debug state, also deprecated synonym for APSR

SPSR

on any processor, in privileged software execution only.

fields

specifies the SPSR or CPSR fields to be moved. fields can be one or more of:

c

control field mask byte, PSR[7:0] (privileged software execution)

x

extension field mask byte, PSR[15:8] (privileged software execution)

s

status field mask byte, PSR[23:16] (privileged software execution)

f

flags field mask byte, PSR[31:24] (privileged software execution).

Show/hideSyntax (ARMv7-M and ARMv6-M only)

You can also use the following syntax on ARMv7 and ARMv6M.

MSR{cond} psr, Rm

where:

cond

is an optional condition code.

Rm

is the source register. Rm must not be PC.

psr

can be any of: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, XPSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Show/hideUsage

In User mode:

  • Use APSR to access condition flags, Q, or GE bits.

  • Writes to unallocated, privileged or execution state bits in the CPSR are ignored. This ensures that User mode programs cannot change to privileged software execution.

If you access the SPSR when in User or System mode, the result is unpredictable.

Show/hideRegister restrictions

You cannot use PC in ARM instructions. You can use SP for Rm in ARM instructions but these are deprecated in ARMv6T2 and above.

You cannot use PC or SP in Thumb instructions.

Show/hideCondition flags

This instruction updates the flags explicitly if the APSR_nzcvq or CPSR_f field is specified.

Show/hideArchitectures

This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above.

There is no 16-bit Thumb version of this instruction.

Show/hideSee also

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