Arithmetic Shift Right, Logical Shift Left, Logical Shift Right, Rotate Right, and Rotate Right with Extend.
These instructions are the preferred synonyms for MOV instructions
with shifted register operands.
Syntaxop{S}{cond}Rd,Rm,Rs
op{S}{cond}Rd,Rm, #sh
RRX{S}{cond} Rd, Rm
where:
opis one of
ASR,LSL,LSR, orROR.Sis an optional suffix. If
Sis specified, the condition code flags are updated on the result of the operation.Rdis the destination register.
Rmis the register holding the first operand. This operand is shifted right.
Rsis a register holding a shift value to apply to the value in
Rmshis a constant shift. The range of values permitted depends on the instruction:
ASRpermitted shifts 1-32
LSLpermitted shifts 0-31
LSRpermitted shifts 1-32
RORpermitted shifts 1-31.
ASR provides the signed value of the contents
of a register divided by a power of two. It copies the sign bit
into vacated bit positions on the left.
LSL provides the value of a register multiplied
by a power of two. LSR provides the unsigned value
of a register divided by a variable power of two. Both instructions
insert zeros into the vacated bit positions.
ROR provides the value of the contents of a register
rotated by a value. The bits that are rotated off the right end
are inserted into the vacated bit positions on the left.
RRX provides the value of the contents of a register
shifted right one bit. The old carry flag is shifted into bit[31].
If the S suffix is present, the old bit[0] is
placed in the carry flag.
You can use SP in these ARM instructions but these are deprecated in ARMv6T2 and above.
You cannot use PC in instructions with the op{S}{cond}
Rd, Rm, Rs syntax. You can use PC for R and dR in
the other syntaxes, but these are deprecated in ARMv6T2 and above. m
If you use PC as Rm
If you use PC as Rd
Execution branches to the address corresponding to the result.
If you use the
Ssuffix, the SPSR of the current mode is copied to the CPSR. You can use this to return from exceptions.Note
The ARM instructions
opS{cond} pc,Rm,#shRRXS{cond} pc,Rmalways disassemble to the preferred formMOVS{.cond} pc,Rm{,shift}
Caution
Do not use the S suffix when using
PC as Rd
You cannot use PC for Rd
If S is specified, these instructions
update the N and Z flags according to the result.
The C flag is unaffected if the shift value is 0. Otherwise, the C flag is updated to the last bit shifted out.
The following forms of these instructions are available in Thumb code, and are 16-bit instructions:
ASRSRd,Rm, #shRdRmASRSRd,Rd,RsRdRsLSLSRd,Rm, #shRdRmLSLSRd,Rd,RsRdRsLSRSRd,Rm, #shRdRmLSRSRd,Rd,RsRdRsRORSRd,Rd,RsRdRs
These ARM instructions are available in all architectures.
These 32-bit Thumb instructions are available in ARMv6T2 and above.
These 16-bit Thumb instructions are available in ARMv4T and above.
There is no 16-bit Thumb RRX instruction.
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