Load and store byte, halfword, word or doublewords to and from Wireless MMX coprocessor registers.
Syntaxop<type>{cond}wRd, [Rn, #{-}offset]{!}
op<type>{cond}wRd, [Rn] {, #{-}offset}
opW{cond}wRd,label
opWwCd, [Rn, #{-}offset]{!}
opWwCd, [Rn] {, #{-}offset}
opD{cond}wRd,label
opDwRd, [Rn, {-}Rm{, LSL #imm4}]{!} ; MMX2 only
opDwRd, [Rn], {-}Rm{, LSL #imm4} ; MMX2 only
where:
opcan be either:
WLDRLoad Wireless MMX Register
WSTRStore Wireless MMX Register.
<type>can be any one of:
BByte
HHalfword
WWord
DDoubleword.
condis an optional condition code.
wRdis the Wireless MMX SIMD data register to load or save.
wCdis the Wireless MMX Status and Control register to load or save.
Rnis the register on which the memory address is based.
offsetis an immediate offset. If offset is omitted, the instruction is a zero offset instruction.
!is an optional suffix. If
!is present, the instruction is a pre-indexed instruction.labelis a PC-relative expression.
labelRmis a register containing a value to be used as the offset.
Rmimm4contains the number of bits to shift
Rm
The assembler also supports the WLDRW and WLDRD literal
load pseudo-instructions, for example:
WLDRW wr0, =0x114
Be aware that:
The assembler cannot load byte and halfword literals. These produce a downgradable error. If downgraded, the instruction is converted to a
WLDRWand a 32-bit literal is generated. This is the same as a byte literal load, but uses a 32-bit word instead.If the literal to be loaded is zero, and the destination is a SIMD Data register, the assembler converts the instruction to a
WZERO.Doubleword loads that are not 8-byte aligned are unpredictable.
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