Preload Data and Preload Instruction. The processor can signal the memory system that a data or instruction load from an address is likely in the near future.
SyntaxPLtype{cond} [Rn{, #offset}]
PLtype{cond} [Rn, +/-Rm{,shift}]
PLtype{cond}label
where:
typecan be one of:
DData address
DWData address with intention to write
IInstruction address.
typeDWif the syntax specifieslabel.condis an optional condition code.
Note
condITinstruction. This is an unconditional instruction in ARM and you must not usecondRnis the register on which the memory address is based.
offsetis an immediate offset. If offset is omitted, the address is the value in
RnRmis a register containing a value to be used as the offset.
shiftis an optional shift.
labelis a PC-relative expression.
The offset is applied to the value in Rn
-4095 to +4095 for ARM instructions
-255 to +4095 for Thumb-2 instructions, when
Rn-4095 to +4095 for Thumb-2 instructions, when
Rn
The assembler calculates the offset from the PC for you. The
assembler generates an error if label
In ARM, the value in RmRnRmRn
The range of shifts permitted is:
LSL#0 to #3 for Thumb-2 instructionsAny one of the following for ARM instructions:
LSL#0 to #31LSR#1 to #32ASR#1 to #32ROR#1 to #31RRX
Rm Rm
RnPL.type{cond}
[Rn, +/-Rm{,
#shift}]
ARM PLD is available in ARMv5TE and above.
32-bit Thumb PLD is available in ARMv6T2 and
above.
PLDW is available only in ARMv7 and above that
implement the Multiprocessing Extensions.
PLI is available only in ARMv7 and above.
There are no 16-bit Thumb PLD, PLDW,
or PLI instructions.
These are hint instructions, and their implementation is optional.
If they are not implemented, they execute as NOPs.
- Concepts
Using the Assembler:
- Reference:
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