Load and Store Multiple registers. Any combination of registers R0 to R15 (PC)
can be transferred in ARM state, but there are some restrictions
in Thumb state.
Syntaxop{addr_mode}{cond}Rn{!},reglist{^}
where:
opcan be either:
LDMLoad Multiple registers
STMStore Multiple registers.
addr_modeis any one of the following:
IAIncrement address After each transfer. This is the default, and can be omitted.
IBIncrement address Before each transfer (ARM only).
DADecrement address After each transfer (ARM only).
DBDecrement address Before each transfer.
You can also use the stack oriented addressing mode suffixes, for example, when implementing stacks.
condis an optional condition code.
Rnis the base register, the ARM register holding the initial address for the transfer.
Rn!is an optional suffix. If
!is present, the final address is written back intoRnreglistis a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.
^is an optional suffix, available in ARM state only. You must not use it in User mode or System mode. It has the following purposes:
If the instruction is
LDM(with any addressing mode) andreglistR15), in addition to the normal multiple register transfer, theSPSRis copied into theCPSR. This is for returning from exception handlers. Use this only from exception modes.Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.
In 32-bit Thumb instructions:
the SP cannot be in the list
the PC cannot be in the list in an
STMinstructionthe PC and LR cannot both be in the list in an
LDMinstructionthere must be two or more registers in the list.
If you write an STM or LDM instruction
with only one register in reglist, the assembler automatically substitutes
the equivalent STR or LDR instruction.
Be aware of this when comparing disassembly listings with source
code.
You can use the --diag_warning 1645 assembler
command line option to check when an instruction substitution occurs.
ARM store instructions can have SP and PC in the reglist but
these instructions that include SP or PC in the reglist are
deprecated in ARMv6T2 and above.
ARM load instructions can have SP and PC in the reglist but
these instructions that include SP in the reglist or
both PC and LR in the reglist are deprecated
in ARMv6T2 and above.
16-bit versions of a subset of these instructions are available in Thumb code.
The following restrictions apply to the 16-bit instructions:
all registers in
reglistRnaddr_modeIA), meaning increment address after each transferwriteback must be specified for
STMinstructionswriteback must be specified for
LDMinstructions whereRnreglist
Note
16-bit Thumb STM instructions with writeback
that specify Rnreglist
In addition, the PUSH and POP instructions
are subsets of the STM and LDM instructions
and can therefore be expressed using the STM and LDM instructions.
Some forms of PUSH and POP are also 16-bit
instructions.
Note
These 16-bit instructions are not available in Thumb-2EE.
A load to the PC causes a branch to the instruction at the address loaded.
In ARMv4, bits[1:0] of the address loaded must be 0b00.
In ARMv5T and above:
bits[1:0] must not be 0b10
if bit[0] is 1, execution continues in Thumb state
if bit[0] is 0, execution continues in ARM state.
In ARM or 16-bit Thumb instructions, if Rnreglist! suffix:
If the instruction is
STM{andaddr_mode}{cond}RnreglistRnOtherwise, the loaded or stored value of
Rcannot be relied upon, so these instructions are not permitted.n
32-bit Thumb instructions are not permitted if Rnreglist! suffix.
STM r5!,{r5,r4,r9} ; value stored for R5 unpredictable
LDMDA r2, {} ; must be at least one register in list
- Concepts
Using the Assembler:
- Reference:
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