Test bits and Test Equivalence.
SyntaxTST{cond}Rn,Operand2
TEQ{cond}Rn,Operand2
where:
condis an optional condition code.
Rnis the ARM register holding the first operand.
Operand2is a flexible second operand.
These instructions test the value in a register against Operand2
The TST instruction performs a bitwise AND operation
on the value in RnOperand2ANDS instruction, except that
the result is discarded.
The TEQ instruction performs a bitwise Exclusive
OR operation on the value in RnOperand2EORS instruction, except that
the result is discarded.
Use the TEQ instruction to test if two values
are equal, without affecting the V or C flags (as CMP does).
TEQ is also useful for testing the sign of a
value. After the comparison, the N flag is the logical Exclusive
OR of the sign bits of the two operands.
In these Thumb instructions, you cannot use SP or PC for RnOperand2.
In these ARM instructions, use of SP or PC is deprecated in ARMv6T2 and above.
For ARM instructions:
if you use PC (
R15) asRnyou cannot use PC for any operand in any data processing instruction that has a register-controlled shift.
These instructions:
update the N and Z flags according to the result
can update the C flag during the calculation of
Operand2do not affect the V flag.
The following form of the TST instruction is
available in Thumb code, and is a 16-bit instruction:
TSTRn,RmRnRm
These ARM instructions are available in all architectures with ARM.
The TST Thumb instruction is available in all
architectures with Thumb.
The TEQ Thumb instruction is available in ARMv6T2
and above.
- Concepts:
- Reference:
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