Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.
Syntaxop{S}{cond}Rd,Rn,Operand2
where:
opis one of:
ANDlogical AND.
ORRlogical OR.
EORlogical Exclusive OR.
BIClogical AND NOT.
ORNlogical OR NOT (Thumb only).
Sis an optional suffix. If
Sis specified, the condition code flags are updated on the result of the operation.condis an optional condition code.
Rdis the destination register.
Rnis the register holding the first operand.
Operand2is a flexible second operand.
The AND, EOR, and ORR instructions
perform bitwise AND, Exclusive OR, and OR operations on the values
in RnOperand2
The BIC (Bit Clear) instruction performs an AND
operation on the bits in RnOperand2
The ORN Thumb instruction performs an OR operation
on the bits in RnOperand2
In certain circumstances, the assembler can substitute BIC for AND, AND for BIC, ORN for ORR,
or ORR for ORN. Be aware of this when
reading disassembly listings.
You cannot use PC (R15) for Rd
You can use PC and SP in these ARM instructions but they are deprecated in ARMv6T2 and above.
If you use PC as Rn
If you use PC as Rd
Execution branches to the address corresponding to the result.
If you use the
Ssuffix, see theSUBS pc,lrinstruction.
You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.
If S is specified, these instructions:
update the N and Z flags according to the result
can update the C flag during the calculation of
Operand2do not affect the V flag.
The following forms of these instructions are available in Thumb code, and are 16-bit instructions:
ANDSRd,Rd,RmRdRmEORSRd,Rd,RmRdRmORRSRd,Rd,RmRdRmBICSRd,Rd,RmRdRm
In the first three cases, it does not matter if you specify OPS Rd, Rm, Rd
AND r9,r2,#0xFF00
ORREQ r2,r0,r5
EORS r0,r0,r3,ROR r6
ANDS r9, r8, #0x19
EORS r7, r11, #0x18181818
BIC r0, r1, #0xab
ORN r7, r11, lr, ROR #4
ORNS r7, r11, lr, ASR #32
- Concepts:
Developing Software for ARM Processors:
- Reference:
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