LDR (PC-relative)

Load register. The address is an offset from the PC.

Show/hideSyntax

LDR{type}{cond}{.W} Rt, label
LDRD{cond} Rt, Rt2, label        ; Doubleword

where:

type

can be any one of:

B

unsigned Byte (Zero extend to 32 bits on loads.)

SB

signed Byte (LDR only. Sign extend to 32 bits.)

H

unsigned Halfword (Zero extend to 32 bits on loads.)

SH

signed Halfword (LDR only. Sign extend to 32 bits.)

-

omitted, for Word.

cond

is an optional condition code.

.W

is an optional instruction width specifier.

Rt

is the register to load or store.

Rt2

is the second register to load or store.

label

is a PC-relative expression.

label must be within a limited distance of the current instruction.

Note

Equivalent syntaxes are available for the STR instruction in ARM code but they are deprecated in ARMv6T2 and above.

Show/hideOffset range and architectures

The assembler calculates the offset from the PC for you. The assembler generates an error if label is out of range.

Table 8 shows the possible offsets between label and the current instruction.

Table 8. PC-relative offsets

InstructionOffset rangeArchitectures
ARM LDR, LDRB, LDRSB, LDRH, LDRSH [a]+/- 4095All
ARM LDRD+/- 255v5TE +
32-bit Thumb LDR, LDRB, LDRSB, LDRH, LDRSH [a]+/- 4095v6T2, v7
32-bit Thumb LDRD+/- 1020 [b]v6T2, v7
16-bit Thumb LDR [c]0-1020 [b]All T

[a] For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state.

[b] Must be a multiple of 4.

[c] Rt must be in the range R0-R7. There are no byte, halfword, or doubleword 16-bit instructions.


Note

In ARMv7-M, LDRD (PC-relative) instructions must be on a word-aligned address.

Show/hideLDR (PC-relative) in Thumb-2

You can use the .W width specifier to force LDR to generate a 32-bit instruction in Thumb-2 code. LDR.W always generates a 32-bit instruction, even if the target could be reached using a 16-bit LDR.

For forward references, LDR without .W always generates a 16-bit instruction in Thumb code, even if that results in failure for a target that could be reached using a 32-bit Thumb-2 LDR instruction.

Show/hideDoubleword register restrictions

For Thumb-2 instructions, you must not specify SP or PC for either Rt or Rt2.

For ARM instructions:

  • Rt must be an even-numbered register

  • Rt must not be LR

  • it is strongly recommended that you do not use R12 for Rt

  • Rt2 must be R(t + 1).

Show/hideUse of SP

In ARM, you can use SP for Rt in LDR word instructions. You can use SP for Rt in LDR non-word ARM instructions but this is deprecated in ARMv6T2 and above.

In Thumb, you can use SP for Rt in LDR word instructions only. All other uses of SP in these instructions are not permitted in Thumb code.

Show/hideSee also

Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489E
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