Load register. The address is an offset from the PC.
Syntax
LDR{type}{cond}{.W} Rt, label
LDRD{cond} Rt, Rt2, label ; Doubleword
where:
typecan be any one of:
Bunsigned Byte (Zero extend to 32 bits on loads.)
SBsigned Byte (
LDRonly. Sign extend to 32 bits.)Hunsigned Halfword (Zero extend to 32 bits on loads.)
SHsigned Halfword (
LDRonly. Sign extend to 32 bits.)-omitted, for Word.
condis an optional condition code.
.Wis an optional instruction width specifier.
Rtis the register to load or store.
Rt2is the second register to load or store.
labelis a PC-relative expression.
label
Note
Equivalent syntaxes are available for the STR instruction
in ARM code but they are deprecated in ARMv6T2 and above.
The assembler calculates the offset from the PC for you. The
assembler generates an error if label
Table 8 shows the possible offsets between label and the current instruction.
Table 8. PC-relative offsets
| Instruction | Offset range | Architectures |
|---|---|---|
ARM LDR, LDRB, LDRSB, LDRH, LDRSH [a] | +/- 4095 | All |
ARM LDRD | +/- 255 | v5TE + |
32-bit Thumb LDR, LDRB, LDRSB, LDRH, LDRSH [a] | +/- 4095 | v6T2, v7 |
32-bit Thumb LDRD | +/- 1020 [b] | v6T2, v7 |
16-bit Thumb LDR [c] | 0-1020 [b] | All T |
[a] For word loads, Rt can be the PC. A load to the PC causes a branch to the address loaded. In ARMv4, bits[1:0] of the address loaded must be 0b00. In ARMv5T and above, bits[1:0] must not be 0b10, and if bit[0] is 1, execution continues in Thumb state, otherwise execution continues in ARM state. [b] Must be a multiple of 4. [c] Rt must be in the range R0-R7. There are no byte, halfword, or doubleword 16-bit instructions. | ||
Note
In ARMv7-M, LDRD (PC-relative) instructions must
be on a word-aligned address.
You can use the .W width specifier to force LDR to
generate a 32-bit instruction in Thumb-2 code. LDR.W always
generates a 32-bit instruction, even if the target could be reached
using a 16-bit LDR.
For forward references, LDR without .W always
generates a 16-bit instruction in Thumb code, even if that results
in failure for a target that could be reached using a 32-bit Thumb-2 LDR instruction.
For Thumb-2 instructions, you must not specify SP or PC for
either RtRt2
For ARM instructions:
RtRtit is strongly recommended that you do not use
R12forRtRt2R(t+ 1).
In ARM, you can use SP for R in tLDR word
instructions. You can use SP for R in tLDR non-word ARM
instructions but this is deprecated in ARMv6T2 and above.
In Thumb, you can use SP for R in tLDR word
instructions only. All other uses of SP in these instructions are
not permitted in Thumb code.
- Concepts:
Using the Assembler:
- Reference:
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