SUBS pc, lr

Exception return, without popping anything from the stack.

Show/hideSyntax

SUBS{cond} pc, lr, #imm               ; ARM and Thumb code
MOVS{cond} pc, lr                     ; ARM and Thumb code
op1S{cond} pc, Rn, #imm               ; ARM code only and is deprecated
op1S{cond} pc, Rn, Rm {, shift}       ; ARM code only and is deprecated
op2S{cond} pc, #imm                   ; ARM code only and is deprecated
op2S{cond} pc, Rm {, shift}           ; ARM code only and is deprecated

where:

op1

is one of ADC, ADD, AND, BIC, EOR, ORN, ORR, RSB, RSC, SBC, and SUB.

op2

is one of MOV and MVN.

cond

is an optional condition code.

imm

is an immediate value. In Thumb code, it is limited to the range 0-255. In ARM code, it is a flexible second operand.

Rn

is the first operand register. ARM deprecates the use of any register except LR.

Rm

is the optionally shifted second or only operand register.

shift

is an optional condition code.

Show/hideUsage

SUBS pc, lr, #imm subtracts a value from the link register and loads the PC with the result, then copies the SPSR to the CPSR.

You can use SUBS pc, lr, #imm to return from an exception if there is no return state on the stack. The value of #imm depends on the exception to return from.

Show/hideNotes

SUBS pc, lr, #imm writes an address to the PC. The alignment of this address must be correct for the instruction set in use after the exception return:

  • For a return to ARM, the address written to the PC must be word-aligned.

  • For a return to Thumb, the address written to the PC must be halfword-aligned.

  • For a return to Jazelle, there are no alignment restrictions on the address written to the PC.

The results of breaking these rules are unpredictable. However, no special precautions are required in software, if the instructions are used to return after a valid exception entry mechanism.

In Thumb, only SUBS{cond} pc, lr, #imm is a valid instruction. MOVS pc, lr is a synonym of SUBS pc, lr, #0. Other instructions are undefined.

In ARM, only SUBS{cond} pc, lr, #imm and MOVS{cond} pc, lr are valid instructions. Other instructions are deprecated in ARMv6T2 and above.

Caution

Do not use these instructions in User mode or System mode. The effect of such an instruction is unpredictable, but the assembler cannot warn you at assembly time.

Show/hideArchitectures

This ARM instruction is available in all versions of the ARM architecture.

This 32-bit Thumb instruction is available in ARMv6T2 and above, except the ARMv7-M architecture.

There is no 16-bit Thumb version of this instruction.

Show/hideSee also

Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489E
Non-ConfidentialID071611