Operand2 as a register with optional shift

You specify an Operand2 register in the form:

Rm {, shift}



is the register holding the data for the second operand.


is an optional constant or register-controlled shift to be applied to Rm. It can be one of:

ASR #n

arithmetic shift right n bits, 1 ≤ n ≤ 32.

LSL #n

logical shift left n bits, 1 ≤ n ≤ 31.

LSR #n

logical shift right n bits, 1 ≤ n ≤ 32.

ROR #n

rotate right n bits, 1 ≤ n ≤ 31.


rotate right one bit, with extend.

type Rs

register-controlled shift is available in ARM code only, where:


is one of ASR, LSL, LSR, ROR.


is a register supplying the shift amount, and only the least significant byte is used.


if omitted, no shift occurs, equivalent to LSL #0.

If you omit the shift, or specify LSL #0, the instruction uses the value in Rm.

If you specify a shift, the shift is applied to the value in Rm, and the resulting 32-bit value is used by the instruction. However, the contents in the register Rm remains unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions.

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