### VMUL{L}, VMLA{L}, and VMLS{L}

`VMUL` (Vector Multiply) multiplies corresponding elements in two vectors, and places the results in the destination vector.

`VMLA` (Vector Multiply Accumulate) multiplies corresponding elements in two vectors, and accumulates the results into the elements of the destination vector.

`VMLS` (Vector Multiply Subtract) multiplies corresponding elements in two vectors, subtracts the results from corresponding elements of the destination vector, and places the final results in the destination vector.

#### Syntax

```V`op`{`cond`}.`datatype` {`Qd`}, `Qn`, `Qm`
```
```V`op`{`cond`}.`datatype` {`Dd`}, `Dn`, `Dm`
```
```V`op`L{`cond`}.`datatype` `Qd`, `Dn`, `Dm`
```

where:

`op`

must be one of:

`MUL`

Multiply

`MLA`

Multiply Accumulate

`MLS`

Multiply Subtract.

`cond`

is an optional condition code.

`datatype`

must be one of:

`I8`, `I16`, `I32`, `F32`

for `VMUL`, `VMLA`, or `VMLS`

`S8`, `S16`, `S32`

for `VMULL`, `VMLAL`, or `VMLSL`

`U8`, `U16`, `U32`

for `VMULL`, `VMLAL`, or `VMLSL`

`P8`

for `VMUL` or `VMULL`.

`Qd, Qn, Qm`

are the destination vector, the first operand vector, and the second operand vector, for a quadword operation.

`Dd, Dn, Dm`

are the destination vector, the first operand vector, and the second operand vector, for a doubleword operation.

`Qd, Dn, Dm`

are the destination vector, the first operand vector, and the second operand vector, for a long operation.

#### See also

Concepts

Using the Assembler:

Reference
 Copyright © 2010-2011 ARM. All rights reserved. ARM DUI 0489F Non-Confidential ID091611 PDF version