V{Q}{R}SHL (by signed variable)

VSHL (Vector Shift Left by signed variable) takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.

The results can be optionally saturated, rounded, or both. The sticky QC flag (FPSCR bit[27]) is set if saturation occurs.

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V{Q}{R}SHL{cond}.datatype {Qd}, Qm, Qn
V{Q}{R}SHL{cond}.datatype {Dd}, Dm, Dn

where:

Q

if present, indicates that If any of the results overflow, they are saturated.

R

if present, indicates that each result is rounded. Otherwise, each result is truncated.

cond

is an optional condition code.

datatype

must be one of S8, S16, S32, S64, U8, U16, U32, or U64.

Qd, Qm, Qn

are the destination vector, the first operand vector, and the second operand vector, for a quadword operation.

Dd, Dm, Dn

are the destination vector, the first operand vector, and the second operand vector, for a doubleword operation.

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Reference
Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489F
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