UND pseudo-instruction

Generate an architecturally undefined instruction. An attempt to execute an undefined instruction causes the Undefined instruction exception. Architecturally undefined instructions are expected to remain undefined.

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UND{cond}{.W} {#expr}

where:

cond

is an optional condition code.

.W

is an optional instruction width specifier.

expr

evaluates to a numeric value. Table 13 shows the range and encoding of expr in the instruction, where Y shows the locations of the bits that encode for expr and V is the 4 bits that encode for the condition code.

If expr is omitted, the value 0 is used.

Table 13. Range and encoding of expr

Instruction

Encoding

Number of bits for expr

Range

ARM

0xV7FYYYFY

16

0-65535

32-bit Thumb

0xF7FYAYFY

12

0-4095

16-bit Thumb

0xDEYY

8

0-255


Show/hideUND in Thumb code

You can use the .W width specifier to force UND to generate a 32-bit instruction in Thumb code on ARMv6T2 and above processors. UND.W always generates a 32-bit instruction, even if expr is in the range 0-255.

Show/hideDisassembly

The encodings that this pseudo-instruction produces disassemble to DCI.

Show/hideSee also

Reference
Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489F
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