VLDR and VSTR (post-increment and pre-decrement)

Pseudo-instructions that load or store extension registers with post-increment and pre-decrement.


There are also VLDR and VSTR instructions without post-increment and pre-decrement.


op{cond}{.size} Fd, [Rn], #offset          ; post-increment
op{cond}{.size} Fd, [Rn, #-offset]!        ; pre-decrement



can be:

  • VLDR - load extension register from memory

  • VSTR - store contents of extension register to memory.


is an optional condition code.


is an optional data size specifier. Must be 32 if Fd is an S register, or 64 if Fd is a D register.


is the extension register to be loaded or saved. For a NEON instruction, it must be a doubleword (Dd) register. For a VFP instruction, it can be either a double precision (Dd) or a single precision (Sd) register.


is the ARM register holding the base address for the transfer.


is a numeric expression that must evaluate to a numeric value at assembly time. The value must be 4 if Fd is an S register, or 8 if Fd is a D register.


The post-increment instruction increments the base address in the register by the offset value, after the transfer. The pre-decrement instruction decrements the base address in the register by the offset value, and then performs the transfer using the new address in the register. These pseudo-instructions assemble to VLDM or VSTM instructions.

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