Where appropriate:

Changed the minor version component of the integer reported by the --version_number option from one to two digits.

ASR, LSL, LSR, ROR, and RRX

ADRL pseudo-instruction

Added SC300 and SC000 to table of --compatible options.

--compatible=name

In the summary table, changed instruction mnemonics from:

Table 15

Added GBLA count to the example.

WHILE and WEND

Changed FPv4_SP to FPv4-SP.

--fpu=name

Added ARM Glossary to other information.

Conventions and feedback

Made changes to ALinknames for MRS, MSR, SEV, SYS, and NOP instructions.

Added links to Memory access instructions in the LDR instruction pages.

Memory access instructions

Changed the restrictions to say that Rt must be even-numbered only in LDREXD and STREXD instructions.

LDREX and STREX

Mentioned the additional cases where SP and PC are deprecated.

Mentioned that deprecation of SP and PC is only in ARMv6T2 and above.

Various instructions

FIELD

Added note that the option is not required if you are using the ARM Compiler toolchain with DS-5.

Introduction

Updated the description of --cpu=name.

--cpu=name

Added the option --execstack.

--execstack

Added the option --no_execstack.

--no_execstack

Added the option --fpmode=none.

--fpmode=model

Updated the description of --show_cmdline.

--show_cmdline

Updated the instruction summary table and footnotes with ARMv7E-M.

Instruction summary

Replaced “profile” with “architecture” when referring to ARMv6-M, ARMv7-M, ARMv7-R, and ARMv7-A in the instruction summary table and in the architecture sections of the instruction descriptions.

Instruction summary

Mentioned register-controlled shift in the description of Operand2.

Operand2 as a register with optional shift

Added register restrictions to ADR (PC-relative).

ADR (PC-relative)

Added register restrictions and deprecation information in LDR and STR (immediate offset).

LDR and STR (immediate offset)

Identified the ARM only instruction syntaxes in LDR and STR (register offset).

LDR and STR (register offset)

Added register restrictions and deprecation information, use of SP, and use of PC in LDR and STR (register offset).

LDR and STR (register offset)

Noted that PC-relative STR is available but deprecated.

LDR (PC-relative)

Added information about deprecation and use of SP in LDR (PC-relative).

LDR (PC-relative)

In Restrictions of reglist in ARM instructions, added that reglist containing both PC and LR in ARM LDM is deprecated.

LDM and STM

Added Restrictions of reglist in ARM instructions.

PUSH and POP

Added register restriction for Rn and moved the statement “Rm must not be PC” to this section.

PLD, PLDW, and PLI

Added restrictions on reglist in LDM and STM.

LDM and STM

Added the statement “must not be PC” for each of the registers in the syntax.

SWP and SWPB

Linked to SUBS pc, lr from Use of PC in ARM instructions.

ADD, SUB, RSB, ADC, SBC, and RSC

Removed the caution against the use of the S suffix when using PC as Rd in User or System mode.

ADD, SUB, RSB, ADC, SBC, and RSC

Mentioned the deprecated instructions that use PC.

ADD, SUB, RSB, ADC, SBC, and RSC

Added more syntaxes that are only present in ARM code and described the additional items in the syntax.

SUBS pc, lr

Documented the valid forms of the SUBS instruction in ARM and Thumb, and added the caution to not use these instructions in User or System mode.

SUBS pc, lr

Linked to SUBS pc, lr from Use of PC in ARM instructions and from See also section.

AND, ORR, EOR, BIC, and ORN

Removed the caution against the use of the S suffix when using PC as Rd in User or System mode.

AND, ORR, EOR, BIC, and ORN

Added Register restrictions section to say Rn cannot be PC in instructions that write back to Rn.

LDC, LDC2, STC, and STC2

Mentioned that Rt cannot be PC.

MCR, MCR2, MCRR, and MCRR2

Mentioned that Rm cannot be PC.

MSR

Linked to SUBS pc, lr from Use of PC in ARM instructions.

MOV and MVN

Removed the caution against the use of the S suffix when using PC as Rd in User or System mode.

MOV and MVN

Mentioned the deprecated instructions that use PC.

MOV and MVN

Mentioned that SP is not permitted in Thumb TST and TEQ instructions, and is deprecated in ARM TST and TEQ instructions.

TST and TEQ

Added that SEL is available in ARMv7E-M.

SEL

Added that Rn must be different from Rd in MUL and MLA before ARMv6.

MUL, MLA, and MLS

Added that Rn must be different from RdLo and RdHi before ARMv6.

UMULL, UMLAL, SMULL, and SMLAL

Added that the Thumb instructions are available in ARMv7E-M.

DBG is available in ARMv6K and above in ARM, and in ARMv6T2 and above in Thumb. Also mentioned that DBG executes as NOP in ARMv6K and ARMv6T2.

DBG

Added figures 4-4 and 4-5 for the operation of VSLI and VSRI.

VSLI and VSRI

Added tables showing the register state before and after operation of VUZP and VZIP.

VUZP, VZIP

Added that n can be a defined relocation name and add a related example in the examples section.

RELOC

Added note for macro workaround when using |.

MACRO and MEND

Clarified the message to say that error generation is during assembly rather than second pass of the assembly.

ASSERT

Added ALIAS directive, and included it in the summary table.

ALIAS

Clarified that n is any integer, and described the examples in the examples sections.

ALIGN

Clarified the description of COMGROUP and GROUP.

AREA

Added note about R_ARM_TARGET1.

AREA

Added link to 8 Byte Stack Alignment in See also section.

REQUIRE8 and PRESERVE8

Added /hardfp and /softfp values to the --apcs option and added link to the --apcs option in the Compiler Reference.

--apcs=qualifier…qualifier

Changed Rn to Rm in “Rd, Rn, Rm and Ra must not be PC”.

USAD8 and USADA8