Load and Store Multiple registers. Any combination of registers R0 to R15 (PC) can be transferred in ARM state, but there are some restrictions in Thumb state.


op{addr_mode}{cond} Rn{!}, reglist{^}



can be either:


Load Multiple registers


Store Multiple registers.


is any one of the following:


Increment address After each transfer. This is the default, and can be omitted.


Increment address Before each transfer (ARM only).


Decrement address After each transfer (ARM only).


Decrement address Before each transfer.

You can also use the stack oriented addressing mode suffixes, for example, when implementing stacks.


is an optional condition code.


is the base register, the ARM register holding the initial address for the transfer. Rn must not be PC.


is an optional suffix. If ! is present, the final address is written back into Rn.


is a list of one or more registers to be loaded or stored, enclosed in braces. It can contain register ranges. It must be comma separated if it contains more than one register or register range.


is an optional suffix, available in ARM state only. You must not use it in User mode or System mode. It has the following purposes:

  • If the instruction is LDM (with any addressing mode) and reglist contains the PC (R15), in addition to the normal multiple register transfer, the SPSR is copied into the CPSR. This is for returning from exception handlers. Use this only from exception modes.

  • Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.

Show/hideRestrictions on reglist in 32-bit Thumb instructions

In 32-bit Thumb instructions:

  • the SP cannot be in the list

  • the PC cannot be in the list in an STM instruction

  • the PC and LR cannot both be in the list in an LDM instruction

  • there must be two or more registers in the list.

If you write an STM or LDM instruction with only one register in reglist, the assembler automatically substitutes the equivalent STR or LDR instruction. Be aware of this when comparing disassembly listings with source code.

You can use the --diag_warning 1645 assembler command line option to check when an instruction substitution occurs.

Show/hideRestrictions on reglist in ARM instructions

ARM store instructions can have SP and PC in the reglist but these instructions that include SP or PC in the reglist are deprecated in ARMv6T2 and above.

ARM load instructions can have SP and PC in the reglist but these instructions that include SP in the reglist or both PC and LR in the reglist are deprecated in ARMv6T2 and above.

Show/hide16-bit instructions

16-bit versions of a subset of these instructions are available in Thumb code.

The following restrictions apply to the 16-bit instructions:

  • all registers in reglist must be Lo registers

  • Rn must be a Lo register

  • addr_mode must be omitted (or IA), meaning increment address after each transfer

  • writeback must be specified for STM instructions

  • writeback must be specified for LDM instructions where Rn is not in the reglist.


16-bit Thumb STM instructions with writeback that specify Rn as the lowest register in the reglist are deprecated in ARMv6T2 and above.

In addition, the PUSH and POP instructions are subsets of the STM and LDM instructions and can therefore be expressed using the STM and LDM instructions. Some forms of PUSH and POP are also 16-bit instructions.


These 16-bit instructions are not available in ThumbEE.

Show/hideLoading to the PC

A load to the PC causes a branch to the instruction at the address loaded.

In ARMv4, bits[1:0] of the address loaded must be 0b00.

In ARMv5T and above:

  • bits[1:0] must not be 0b10

  • if bit[0] is 1, execution continues in Thumb state

  • if bit[0] is 0, execution continues in ARM state.

Show/hideLoading or storing the base register, with writeback

In ARM or 16-bit Thumb instructions, if Rn is in reglist, and writeback is specified with the ! suffix:

  • If the instruction is STM{addr_mode}{cond} and Rn is the lowest-numbered register in reglist, the initial value of Rn is stored. These instructions are deprecated in ARMv6T2 and above.

  • Otherwise, the loaded or stored value of Rn cannot be relied upon, so these instructions are not permitted.

32-bit Thumb instructions are not permitted if Rn is in reglist, and writeback is specified with the ! suffix.


    LDM     r8,{r0,r2,r9}      ; LDMIA is a synonym for LDM
    STMDB   r1!,{r3-r6,r11,r12}

Show/hideIncorrect examples

    STM     r5!,{r5,r4,r9} ; value stored for R5 unknown
    LDMDA   r2, {}         ; must be at least one register in list

Show/hideSee also

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