MOV and MVN

Move and Move Not.

Show/hideSyntax

MOV{S}{cond} Rd, Operand2
MOV{cond} Rd, #imm16
MVN{S}{cond} Rd, Operand2

where:

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Operand2

is a flexible second operand.

imm16

is any value in the range 0-65535.

Show/hideUsage

The MOV instruction copies the value of Operand2 into Rd.

The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value, and places the result into Rd.

In certain circumstances, the assembler can substitute MVN for MOV, or MOV for MVN. Be aware of this when reading disassembly listings.

Show/hideUse of PC and SP in 32-bit Thumb MOV and MVN

You cannot use PC (R15) for Rd, or in Operand2, in 32-bit Thumb MOV or MVN instructions. With the following exceptions, you cannot use SP (R13) for Rd, or in Operand2:

  • MOV{cond}.W Rd, SP, where Rd is not SP

  • MOV{cond}.W SP, Rm, where Rm is not SP.

Show/hideUse of PC and SP in 16-bit Thumb

You can use PC or SP in 16-bit Thumb MOV{cond} Rd, Rm instructions but these instructions in which both Rd and Rm are SP or PC are deprecated in ARMv6T2 and above.

You cannot use PC or SP in any other MOV{S} or MVN{S} 16-bit Thumb instructions.

Show/hideUse of PC and SP in ARM MOV and MVN

You cannot use PC for Rd or any operand in any data processing instruction that has a register-controlled shift.

In instructions without register-controlled shift, use of PC is deprecated except the following cases:

  • MOVS PC, LR

  • MOV PC, Rm when Rm is not PC or SP

  • MOV Rd, PC when Rd is not PC or SP.

You can use SP for Rd or Rm. But these are deprecated except the following cases:

  • MOV SP, Rm when Rm is not PC or SP

  • MOV Rd, SP when Rd is not PC or SP.

Note

  • You cannot use PC for Rd in MOV Rd, #imm16 if the #imm16 value is not a permitted Operand2 value. You can use PC in forms with Operand2 without register-controlled shift.

  • The deprecation of PC and SP in ARM instructions only apply to ARMv6T2 and above.

If you use PC as Rm, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

Show/hideCondition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2

  • do not affect the V flag.

Show/hide16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

MOVS Rd, #imm

Rd must be a Lo register. imm range 0-255.

MOVS Rd, Rm

Rd and Rm must both be Lo registers.

MOV Rd, Rm

In architectures before ARMv6, either Rd or Rm, or both, must be a Hi register. In ARMv6 and above, this restriction does not apply.

Show/hideArchitectures

The #imm16 form of the ARM instruction is available in ARMv6T2 and above. The other forms of the ARM instruction are available in all versions of the ARM architecture.

These 32-bit Thumb instructions are available in ARMv6T2 and above.

These 16-bit Thumb instructions are available in all T variants of the ARM architecture.

Show/hideExample

    MVNNE   r11, #0xF000000B ; ARM only. This immediate value is not
                             ; available in T2.

Show/hideIncorrect example

    MVN     pc,r3,ASR r0     ; PC not permitted with register-controlled shift

Show/hideSee also

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