AND, ORR, EOR, BIC, and ORN

Logical AND, OR, Exclusive OR, Bit Clear, and OR NOT.

Show/hideSyntax

op{S}{cond} Rd, Rn, Operand2

where:

op

is one of:

AND

logical AND.

ORR

logical OR.

EOR

logical Exclusive OR.

BIC

logical AND NOT.

ORN

logical OR NOT (Thumb only).

S

is an optional suffix. If S is specified, the condition code flags are updated on the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand.

Show/hideUsage

The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2.

The BIC (Bit Clear) instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

The ORN Thumb instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2.

In certain circumstances, the assembler can substitute BIC for AND, AND for BIC, ORN for ORR, or ORR for ORN. Be aware of this when reading disassembly listings.

Show/hideUse of PC in 32-bit Thumb instructions

You cannot use PC (R15) for Rd or any operand in any of these instructions.

Show/hideUse of PC and SP in ARM instructions

You can use PC and SP in these ARM instructions but they are deprecated in ARMv6T2 and above.

If you use PC as Rn, the value used is the address of the instruction plus 8.

If you use PC as Rd:

  • Execution branches to the address corresponding to the result.

  • If you use the S suffix, see the SUBS pc,lr instruction.

You cannot use PC for any operand in any data processing instruction that has a register-controlled shift.

Show/hideCondition flags

If S is specified, these instructions:

  • update the N and Z flags according to the result

  • can update the C flag during the calculation of Operand2

  • do not affect the V flag.

Show/hide16-bit instructions

The following forms of these instructions are available in Thumb code, and are 16-bit instructions:

ANDS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

EORS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

ORRS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

BICS Rd, Rd, Rm

Rd and Rm must both be Lo registers.

In the first three cases, it does not matter if you specify OPS Rd, Rm, Rd. The instruction is the same.

Show/hideExamples

    AND     r9,r2,#0xFF00
    ORREQ   r2,r0,r5
    EORS    r0,r0,r3,ROR r6
    ANDS    r9, r8, #0x19
    EORS    r7, r11, #0x18181818 
    BIC     r0, r1, #0xab
    ORN     r7, r11, lr, ROR #4
    ORNS    r7, r11, lr, ASR #32

Show/hideIncorrect example

    EORS    r0,pc,r3,ROR r6     ; PC not permitted with register
                                ; controlled shift

Show/hideSee also

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