SMLALD and SMLSLD

Dual 16-bit Signed Multiply with Addition or Subtraction of products and 64-bit Accumulation.

Show/hideSyntax

op{X}{cond} RdLo, RdHi, Rn, Rm

where:

op

is one of:

SMLALD

Dual multiply, accumulate sum of products.

SMLSLD

Dual multiply, accumulate difference of products.

X

is an optional parameter. If X is present, the most and least significant halfwords of the second operand are exchanged before the multiplications occur.

cond

is an optional condition code.

RdLo, RdHi

are the destination registers for the 64-bit result. They also hold the 64-bit accumulate operand. RdHi and RdLo must be different registers.

Rn, Rm

are the registers holding the operands.

Show/hideOperation

SMLALD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then adds both products to the value in RdLo, RdHi and stores the sum to RdLo, RdHi.

SMLSLD multiplies the bottom halfword of Rn with the bottom halfword of Rm, and the top halfword of Rn with the top halfword of Rm. It then subtracts the second product from the first, adds the difference to the value in RdLo, RdHi, and stores the result to RdLo, RdHi.

Show/hideRegister restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Show/hideCondition flags

These instructions do not change the flags.

Show/hideArchitectures

These ARM instructions are available in ARMv6 and above.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

Show/hideExamples

    SMLALD      r10, r11, r5, r1
    SMLSLD      r3, r0, r5, r1

Show/hideSee also

Reference
Copyright © 2010-2011 ARM. All rights reserved.ARM DUI 0489F
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