ARM Compiler toolchain Assembler Reference: SMULWy and SMLAWy

SMULW`y` and SMLAW`y`

Signed Multiply Wide and Signed Multiply-Accumulate Wide, with one 32-bit and one 16-bit operand, providing the top 32-bits of the result.

Syntax

SMULW<y>{cond} {Rd}, Rn, Rm

SMLAW<y>{cond} Rd, Rn, Rm, Ra

where:

<y>: is either B or T. B means use the bottom half (bits [15:0]) of Rm, T means use the top half (bits [31:16]) of Rm.
cond: is an optional condition code.
Rd: is the destination register.
Rn, Rm: are the registers holding the values to be multiplied.
Ra: is the register holding the value to be added.

Usage

SMULWy multiplies the signed integer from the selected half of Rm by the signed integer from Rn, and places the upper 32-bits of the 48-bit result in Rd.

SMLAWy multiplies the signed integer from the selected half of Rm by the signed integer from Rn, adds the 32-bit result to the 32-bit value in Ra, and places the result in Rd.

Register restrictions

You cannot use PC for any register.

You can use SP in ARM instructions but these are deprecated in ARMv6T2 and above. You cannot use SP in Thumb instructions.

Condition flags

These instructions do not affect the N, Z, C, or V flags.

If overflow occurs in the accumulation, SMLAWy sets the Q flag.

Architectures

These ARM instructions are available in ARMv6 and above, and E variants of ARMv5T.

These 32-bit Thumb instructions are available in ARMv6T2 and above. For the ARMv7-M architecture, they are only available in an ARMv7E-M implementation.

There are no 16-bit Thumb versions of these instructions.

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SMULWy and SMLAWy